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1. general description the lpc408x/7x is an arm cortex-m4 based digital signal controller for embedded applications requiring a high level of integration and low power dissipation. the arm cortex-m4 is a next generation core that offers system enhancements such as low power consumption, enhanced debug feat ures, and a high level of support block integration. the arm cortex-m4 cpu incorpor ates a 3-stage pipeline, uses a harvard architecture with sepa rate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. the arm cortex-m4 supports single-cycle digital signal processing and simd instructions. a hardware floating-point processor is integrated in the core for several versions of the part. the lpc408x/7x adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash. the lpc408x/7x is targeted to operate at up to 120 mhz cpu frequency. the peripheral complement of the lpc408x/7 x includes up to 512 kb of flash program memory, up to 96 kb of sram data memory , up to 4032 byte of eeprom data memory, external memory controller (emc), lcd, et hernet, usb device/host/otg, an spi flash interface (spifi), a general purpose dma controller, five uarts, three ssp controllers, three i 2 c-bus interfaces, a quadrature encoder in terface, four general purpose timers, two general purpose pwms with six outputs each and one motor control pwm, an ultra-low power rtc with separate battery supply and event recorder, a windowed watchdog timer, a crc calculation engine and up to 165 general purpose i/o pins. the analog peripherals include one eight-ch annel 12-bit adc, two analog comparators, and a dac. the pinout of lpc408x/7x is intended to allow pin fu nction compatibility with the lpc24xx/23xx as well as the lpc178x/7x families. 2. features and benefits ? functional replacement for lpc23xx/24 xx and lpc178x/7x family devices. ? arm cortex-m4 core: ? arm cortex-m4 processor, running at frequencies of up to 120 mhz. ? arm cortex-m4 built-in memory protection unit (mpu) supporting eight regions. ? arm cortex-m4 built-in nested vectored interrupt controller (nvic). ? hardware floating- point unit (not all versions). ? non-maskable inte rrupt (nmi) input. lpc408x/7x 32-bit arm cortex-m4 mcu; up to 512 kb flash, 96 kb sram; usb device/host/otg; e thernet; lcd; emc; spifi rev. 1 ? 17 september 2012 objective data sheet
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 2 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? jtag and serial wire debug (swd), serial trace, eight breakpoi nts, and four watch points. ? system tick timer. ? system: ? multilayer ahb matrix interc onnect provides a separate bus for each ahb master. ahb masters include the cpu, and general purpose dma controller. this interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time. ? split apb bus allows for higher throughput with fewer stalls between the cpu and dma. a single level of write buffering allows the cpu to continue without waiting for completion of apb writes if the apb was not already busy. ? embedded trace macrocell (etm) module supports real-time trace. ? boundary scan for simplified board testing. ? memory: ? 512 kb on-chip flash program memory with in-system programming (isp) and in-application programming (iap) capabilities. the combination of an enhanced flash memory accelerator and location of the flash memory on the cpu local code/data bus provides high code performance from flash. ? up to 96 kb on-chip sram includes: 64 kb of main sram on the cpu with local code/data bus for high-performance cpu access. two 16 kb peripheral sram blocks with separate access paths for higher throughput. these sram blocks may be used for dma memory as well as for general purpose instruction and data storage. ? up to 4032 byte on-chip eeprom. ? lcd controller, supporting both super-twisted nematic (stn) and thin-film transistors (tft) displays. ? dedicated dma controller. ? selectable display resolution (up to 1024 ? 768 pixels). ? supports up to 24-bit true-color mode. ? external memory controller (emc) provides support for asynchronous static memory devices such as ram, rom and flash, as well as dynamic memories such as single data rate sdram. ? eight channel general purpose dma controller (gpdma) on the ahb multilayer matrix that can be used with the ssp, i2s, uart, crc engine, analog-to-digital and digital-to-analog converter peripherals, timer match signals, gpio, and for memory-to-memory transfers. ? serial interfaces: ? quad spi flash interface (spifi) with fo ur lanes and up to 40 mb per second. ? ethernet mac with mii/rmii interface and associated dma controller. these functions reside on an independent ahb. ? usb 2.0 full-speed dual port device/ho st/otg controller with on-chip phy and associated dma controller. ? five uarts with fractional baud rate generation, internal fifo, dma support, and rs-485/eia-485 support. one uart (uart1) has full modem control i/o, and one uart (usart4) supports irda, synchronous mode, and a smart card mode conforming to iso7816-3.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 3 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? three ssp controllers with fifo and multi- protocol capabilities. the ssp interfaces can be used with the gpdma controller. ? three enhanced i 2 c-bus interfaces, one with a true open-drain output supporting the full i 2 c-bus specification and fast-mode plus with data rates of 1 mbit/s, two with standard port pins. enhancements include multiple address recognition and monitor mode. ? i 2 s (inter-ic sound) interface for digital audio input or output. it can be used with the gpdma. ? can controller with two channels. ? digital peripherals: ? sd/mmc memory card interface. ? up to 165 general purpose i/o (gpio) pins depending on the packaging, with configurable pull-up/down resistors, op en-drain mode, and repeater mode. all gpios are located on an ahb bus for fast access and support cortex-m4 bit-banding. gpios can be accessed by the general purpose dma controller. any pin of ports 0 and 2 can be used to generate an interrupt. ? two external interrupt inputs configurable as edge/level sensitive. all pins on port 0 and port 2 can be used as edge sensitive interrupt sources. ? four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. each timer block has an external count input. specific timer events can be selected to generate dma requests. ? quadrature encoder interfac e that can monitor one external quadrature encoder. ? two standard pwm/timer blocks with external count input option. ? one motor control pwm with suppor t for three-phase motor control. ? real-time clock (rtc) with a separate power domain. the rtc is clocked by a dedicated rtc oscillator. the rtc block includes 20 bytes of battery-powered backup registers, allowing syst em status to be stored when the rest of the chip is powered off. battery power can be supplied from a standard 3 v lithium button cell. the rtc will continue working when the batter y voltage drops to as low as 2.1 v. an rtc interrupt can wake up the cpu from any reduced power mode. ? event recorder that can capture the cloc k value when an event occurs on any of three inputs. the event identification a nd the time it occurred are stored in registers. the event recorder is lo cated in the rtc power domain and can therefore operate as long as there is rtc power. ? windowed watchdog timer (wwdt). window ed operation, dedicated internal oscillator, watchdog warning in terrupt, and sa fety features. ? crc engine block can calculate a crc on supplied data using one of three standard polynomials. the crc engine can be used in conjunction with the dma controller to generate a crc without cpu involvement in the data transfer. ? analog peripherals: ? 12-bit analog-to-digital converter (adc) with input multiplexing among eight pins, conversion rates up to 400 khz, and multiple result registers. the 12-bit adc can be used with the gpdma controller. ? 10-bit digital-to-analog converter (dac) with dedicated conversion timer and dma support. ? two analog comparators. ? power control:
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 4 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? four reduced power modes: sleep, deep-sleep, power-down, and deep power-down. ? the wake-up interrupt controller (wic) allows the cpu to automatically wake up from any priority interrup t that can occur while the clocks are stopped in deep-sleep, power- down, and deep power-down modes. ? processor wake-up from power-down mode via any interrupt able to operate during power-down mode (includes external interrupts, rtc interrupt, port0/2 pin interrupt, and nmi). ? brownout detect with separate threshold for interrupt and forced reset. ? on-chip power-on reset (por). ? clock generation: ? clock output function that can reflect the main oscilla tor clock, irc clock, rtc clock, cpu clock, usb clock, or the watchdog timer clock. ? on-chip crystal oscillator with an op erating range of 1 mhz to 25 mhz. ? 12 mhz internal rc oscillato r (irc) trimmed to 1% accura cy that can optionally be used as a system clock. ? an on-chip pll allows cpu operation up to the maximum cpu rate without the need for a high-frequ ency crystal. may be run from the main oscillator or the internal rc oscillator. ? a second, dedicated pll may be used for usb interface in order to allow added flexibility for the main pll settings. ? versatile pin function selection feature allows many possibilities for using on-chip peripheral functions. ? unique device serial number for identification purposes. ? single 3.3 v power supply (2.4 v to 3.6 v). temperature range of ? 40 ? c to 85 ? c. ? available as lqfp208, tfbga208, tfbga180, lqfp144, and lqfp80 package. 3. applications ? communications: ? point-of-sale terminals, web se rvers, multi-protocol bridges ? industrial/medical: ? automation controllers, application control, robotics control, hvac, plc, inverters, circuit breakers, medical scanning, security monitoring, motor drive, video intercom ? consumer/appliance: ? audio, mp3 decoders, alarm systems, displays, printers, scanners, small appliances, fitness equipment ? automotive: ? after-market, car alarms, gps/fleet monitors
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 5 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 4. ordering information table 1. ordering information type number package name description version lpc4088 lpc4088fbd208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 ? 28 ? 1.4 mm sot459-1 LPC4088FET208 tfbga208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 ? 15 ? 0.7 mm sot950-1 lpc4088fet180 tfbga180 thin fine-pitch ball grid array package; 180 balls; body 12 ? 12 ? 0.8 mm sot570-2 lpc4088fbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4078 lpc4078fbd208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 ? 28 ? 1.4 mm sot459-1 lpc4078fet208 tfbga208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 ? 15 ? 0.7 mm sot950-1 lpc4078fet180 tfbga180 thin fine-pitch ball grid array package; 180 balls; body 12 ? 12 ? 0.8 mm sot570-2 llpc4078fbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4078fbd80 lqfp80 plastic low-profile quad package; 80 leads; body 12 ? 12 ? 1.4 mm sot315-1 lpc4076 lpc4076fet180 tfbga180 thin fine-pitch ball grid array package; 180 balls; body 12 ? 12 ? 0.8 mm sot570-2 lpc4076fbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4074 lpc4074fbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4074fbd80 lqfp80 plastic low-profile quad package; 80 leads; body 12 ? 12 ? 1.4 mm sot315-1 lpc4072 lpc4072fbd80 lqfp80 plastic low-profile quad package; 80 leads; body 12 ? 12 ? 1.4 mm sot315-1 table 2. ordering options type number flash (kb) sram (kb) eeprom (b) emc bus width (bit) lcd ethernet usb uart qei sd/mmc comparator fpu package lpc4088 lpc4088fbd208 512 96 4032 32 yes yes h/o/d 5 yes yes yes yes lqfp208 LPC4088FET208 512 96 4032 32 yes yes h/o/d 5 yes yes yes yes tfbga208 lpc4088fet180 512 96 4032 16 yes yes h/o/d 5 yes yes yes yes tfbga180 lpc4088fbd144 512 96 4032 8 yes yes h/o/d 5 yes yes yes yes lqfp144 lpc4078 lpc4078fbd208 512 96 4032 32 no yes h/o/d 5 yes yes yes yes lqfp208 lpc4078fet208 512 96 4032 32 no yes h/o/d 5 yes yes yes yes tfbga208 lpc4078fet180 512 96 4032 16 no yes h/o/d 5 yes yes yes yes tfbga180 lpc4078fbd144 512 96 4032 8 no yes h/o/d 5 yes yes yes yes lqfp144 lpc4078fbd80 512 96 4032 - no yes h/o/d 5 yes yes yes yes lqfp80
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 6 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller lpc4076 lpc4076fet180 256 80 2048 16 no yes h/o/d 5 yes yes yes yes tfbga180 lpc4076fbd144 256 80 2048 8 no yes h/o/d 5 yes yes yes yes lqfp144 lpc4074 lpc4074fbd144 128 40 2048 - no no d 4 no no no no lqfp144 lpc4074fbd80 128 40 2048 - no no d 4 no no no no bga80 lpc4072 lpc4072fbd80 64 24 2048 - no no d 4 no no no no lqfp80 table 2. ordering options type number flash (kb) sram (kb) eeprom (b) emc bus width (bit) lcd ethernet usb uart qei sd/mmc comparator fpu package
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 7 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 5. block diagram (1) not available on all parts. fig 1. block diagram sram 96/80/ 40/24 kb arm cortex-m4 test/debug interface emulation trace module flash accelerator flash 512/256/128/64 kb gpdma controller i-code bus d-code bus system bus ahb to apb bridge 0 high-speed gpio ahb to apb bridge 1 4032 b/ 2048 b eeprom clock generation, power control, system functions clocks and controls jtag interface debug port ssp0/2 usart4 (1) uart2/3 system control 2 x analog comparator (1) ssp1 uart0/1 i 2 c0/1 can 0/1 timer 0/1 windowed wdt 12-bit adc pwm0/1 pin connect gpio interrupt control rtc backup registers event recorder 32 khz oscillator apb slave group 1 apb slave group 0 rtc power domain lpc408x/7x master ethernet (1) master usb device/ host (1) /otg (1) master 002aag491 slave slave crc slave spifi slave slave slave slave rom emc (1) slave slave lcd (1) slave multilayer ahb matrix i 2 c2 timer2/3 dac i 2 s quadrature encoder (1) motor control pwm mpu fpu (1) sd/mmc (1) = connected to gpdma
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 8 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 6. pinning information 6.1 pinning fig 2. pin configuration (lqfp208) fig 3. pin configuration (tfbga208) lpc408x/7xfbd208 156 53 104 208 157 105 1 52 002aag732 002aag733 lpc408x/7x transparent top view ball a1 index area u t r p n m k h l j g f e d c a b 24681012 13 14 15 17 16 1357911
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 9 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller fig 4. pin configuration (tfbga180) fig 5. pin configuration (lqfp144) fig 6. pin configuration (lqfp80) 002aag734 lpc408x/7x 2 4 6 8 10 12 13 14 1357911 ball a1 index area p n m l k j g e h f d c b a transparent top view lpc408x/7x 108 37 72 144 109 73 1 36 002aag735 40 1 20 60 41 21 61 80 002aag865 lpc408x/7x
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 10 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 6.2 pin description i/o pins on the lpc408x/7x are 5v tolerant and have input hyster esis unless otherwise indicated in the table below. crystal pins, power pins, and reference voltage pins are not 5v tolerant. in addition, when pins are selected to be adc inputs, they are no longer 5v tolerant and the input voltage must be limited to the voltage at the adc positive reference pin (vrefp). all port pins pn[m] are multiplexed, an d the multiplexed functions appear in ta b l e 3 in the order defined by the func bits of the corres ponding iocon register up to the highest used function number. each port pin can support up to eight multiplexed functions. iocon register func values which are reserved are noted as ?r? in the pin configuration table. table 3. pin description not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description p0[0] to p0[31] i/o port 0: port 0 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 0 pins depends upon the pin function selected via the pin connect block. p0[0] 94u15m106637 [3] i; pu i/o p0[0] ? general purpose digital input/output pin. i can_rd1 ? can1 receiver input. o u3_txd ? transmitter output for uart3. i/o i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i2c pad). o u0_txd ? transmitter output for uart0. p0[1] 96t14n116738 [3] i; pu i/o p0[1] ? general purpose digital input/output pin. o can_td1 ? can1 transmitter output. i u3_rxd ? receiver input for uart3. i/o i2c1_scl ? i 2 c1 clock input/output (this pin does not use a specialized i2c pad). i u0_rxd ? receiver input for uart0. p0[2] 202 c4 d5 141 79 [3] i; pu i/o p0[2] ? general purpose digital input/output pin. o u0_txd ? transmitter output for uart0. o u3_txd ? transmitter output for uart3. p0[3] 204 d6 a3 142 80 [3] i; pu i/o p0[3] ? general purpose digital input/output pin. i u0_rxd ? receiver input for uart0. i u3_rxd ? receiver input for uart3.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 11 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p0[4] 168 b12 a11 116 - [3] i; pu i/o p0[4] ? general purpose digital input/output pin. i/o i2s_rx_sck ? i 2 s receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i can_rd2 ? can2 receiver input. i t2_cap0 ? capture input for timer 2, channel 0. - r ? function reserved. i/o cmp_rosc ? comparator relaxation oscillator for 555 timer applications. - r ? function reserved. o lcd_vd[0] ? lcd data. p0[5] 166 c12 b11 115 - [3] i; pu i/o p0[5] ? general purpose digital input/output pin. i/o i2s_rx_ws ? i 2 s receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . o can_td2 ? can2 transmitter output. i t2_cap1 ? capture input for timer 2, channel 1. - r ? function reserved. i cmp_reset ? comparator reset. - r ? function reserved. o lcd_vd[1] ? lcd data. p0[6] 164 d13 d11 113 64 [3] i; pu i/o p0[6] ? general purpose digital input/output pin. i/o i2s_rx_sda ? i 2 s receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o ssp1_ssel ? slave select for ssp1. o t2_mat0 ? match output for timer 2, channel 0. o u1_rts ? request to send output for uart1. can also be configured to be an rs-485 /eia-485 output enable signal for uart1. i/o cmp_rosc ? comparator relaxation oscillator for 555 timer applications. - r ? function reserved. o lcd_vd[8] ? lcd data. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 12 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p0[7] 162 c13 b12 112 63 [4] i; ia i/o p0[7] ? general purpose digital input/output pin. i/o i2s_tx_sck ? i 2 s transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i/o ssp1_sck ? serial clock for ssp1. o t2_mat1 ? match output for timer 2, channel 1. i rtc_ev0 ? event input 0 to even t monitor/ recorder. i cmp_vref ? comparator reference voltage. - r ? function reserved. o lcd_vd[9] ? lcd data. p0[8] 160 a15 c12 111 62 [4] i; ia i/o p0[8] ? general purpose digital input/output pin. i/o i2s_tx_ws ? i 2 s transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o ssp1_miso ? master in slave out for ssp1. o t2_mat2 ? match output for timer 2, channel 2. i rtc_ev1 ? event input 1 to even t monitor/ recorder. i cmp1_in[3] ? comparator 1, input 3. - r ? function reserved. o lcd_vd[16] ? lcd data. p0[9] 158 c14 a13 109 61 [4] i; ia i/o p0[9] ? general purpose digital input/output pin. i/o i2s_tx_sda ? i 2 s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o ssp1_mosi ? master out slave in for ssp1. o t2_mat3 ? match output for timer 2, channel 3. i rtc_ev2 ? event input 2 to even t monitor/ recorder. i cmp1_in[2] ? comparator 1, input 2. - r ? function reserved. o lcd_vd[17] ? lcd data. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 13 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p0[10] 98 t15 l10 69 39 [3] i; pu i/o p0[10] ? general purpose digital input/output pin. o u2_txd ? transmitter output for uart2. i/o i2c2_sda ? i 2 c2 data input/output (this pin does not use a specialized i2c pad). o t3_mat0 ? match output for timer 3, channel 0. - r ? function reserved. - r ? function reserved. - r ? function reserved. o lcd_vd[5] ? lcd data. p0[11] 100 r14 p12 70 40 [3] i; pu i/o p0[11] ? general purpose digital input/output pin. i u2_rxd ? receiver input for uart2. i/o i2c2_scl ? i 2 c2 clock input/output (this pin does not use a specialized i2c pad). o t3_mat1 ? match output for timer 3, channel 1. - r ? function reserved. - r ? function reserved. - r ? function reserved. o lcd_vd[10] ? lcd data. p0[12] 41 r1 j4 29 - [5] i; pu i/o p0[12] ? general purpose digital input/output pin. o usb_ppwr2 ? port power enable signal for usb port 2. i/o ssp1_miso ? master in slave out for ssp1. i adc0_in[6] ? a/d converter 0, input 6. when configured as an adc input, the digital function of the pin must be disabled. p0[13] 45 r2 j5 32 - [5] i; pu i/o p0[13] ? general purpose digital input/output pin. o usb_up_led2 ? usb port 2 goodlink led indicator. it is low when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. it is high when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. it transitions between low and high (flashes) when the host is enabled and detects activity on the bus. i/o ssp1_mosi ? master out slave in for ssp1. i adc0_in[7] ? a/d converter 0, input 7. when configured as an adc input, the digital function of the pin must be disabled. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 14 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p0[14] 69 t7 m5 48 - [3] i; pu i/o p0[14] ? general purpose digital input/output pin. o usb_hsten2 ? host enabled status for usb port 2. i/o ssp1_ssel ? slave select for ssp1. o usb_connect2 ? softconnect control for usb port 2. signal used to switch an external 1.5 k ? resistor under software control. used with the softconnect usb feature. p0[15] 128 j16 h13 89 47 [3] i; pu i/o p0[15] ? general purpose digital input/output pin. o u1_txd ? transmitter output for uart1. i/o ssp0_sck ? serial clock for ssp0. - r ? function reserved. - r ? function reserved. i/o spifi_io[2] ? data bit 0 for spifi. p0[16] 130 j14 h14 90 48 [3] i; pu i/o p0 [16] ? general purpose digital input/output pin. i u1_rxd ? receiver input for uart1. i/o ssp0_ssel ? slave select for ssp0. - r ? function reserved. - r ? function reserved. i/o spifi_io[3] ? data bit 0 for spifi. p0[17] 126 k17 j12 87 46 [3] i; pu i/o p0[17] ? general purpose digital input/output pin. i u1_cts ? clear to send input for uart1. i/o ssp0_miso ? master in slave out for ssp0. - r ? function reserved. - r ? function reserved. i/o spifi_io[1] ? data bit 0 for spifi. p0[18] 124 k15 j13 86 45 [3] i; pu i/o p0[18] ? general purpose digital input/output pin. i u1_dcd ? data carrier detect input for uart1. i/o ssp0_mosi ? master out slave in for ssp0. - r ? function reserved. - r ? function reserved. i/o spifi_io[0] ? data bit 0 for spifi. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 15 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p0[19] 122 l17 j10 85 - [3] i; pu i/o p0[19] ? general purpose digital input/output pin. i u1_dsr ? data set ready input for uart1. o sd_clk ? clock output line for sd card interface. i/o i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i2c pad). - r ? function reserved. - r ? function reserved. - r ? function reserved. o lcd_vd[13] ? lcd data. p0[20] 120 m17 k14 83 - [3] i; pu i/o p0[20] ? general purpose digital input/output pin. o u1_dtr ? data terminal ready output for uart1. can also be configured to be an rs-485/eia-485 output enable signal for uart1. i/o sd_cmd ? command line for sd card interface. i/o i2c1_scl ? i 2 c1 clock input/output (this pin does not use a specialized i2c pad). - r ? function reserved. - r ? function reserved. - r ? function reserved. o lcd_vd[14] ? lcd data. p0[21] 118 m16 k11 82 - [3] i; pu i/o p0[21] ? general purpose digital input/output pin. i u1_ri ? ring indicator input for uart1. o sd_pwr ? power supply enable for external sd card power supply. o u4_oe ? rs-485/eia-485 output enable signal for uart4. i can_rd1 ? can1 receiver input. i/o u4_sclk ? usart 4 clock input or output in synchronous mode. p0[22] 116 n17 l14 80 44 [6] i; pu i/o p0[22] ? general purpose digital input/output pin. o u1_rts ? request to send output for uart1. can also be configured to be an rs-485 /eia-485 output enable signal for uart1. i/o sd_dat[0] ? data line 0 for sd card interface. o u4_txd ? transmitter output for usart4 (input/output in smart card mode). o can_td1 ? can1 transmitter output. o spifi_clk ? clock output for spifi. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 16 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p0[23] 18 h1 f5 13 - [5] i; pu i/o p0[23] ? general purpose digital input/output pin. i adc0_in[0] ? a/d converter 0, input 0. when configured as an adc input, the digital function of the pin must be disabled. i/o i2s_rx_sck ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i t3_cap0 ? capture input for timer 3, channel 0. p0[24] 16 g2 e1 11 - [5] i; pu i/o p0[24] ? general purpose digital input/output pin. i adc0_in[1] ? a/d converter 0, input 1. when configured as an adc input, the digital function of the pin must be disabled. i/o i2s_rx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i t3_cap1 ? capture input for timer 3, channel 1. p0[25] 14 f1 e4 10 7 [5] i; pu i/o p0[25] ? general purpose digital input/output pin. i adc0_in[2] ? a/d converter 0, input 2. when configured as an adc input, the digital function of the pin must be disabled. i/o i2s_rx_sda ? receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o u3_txd ? transmitter output for uart3. p0[26] 12 e1 d1 8 6 [7] i; pu i/o p0[26] ? general purpose digital input/output pin. i adc0_in[3] ? a/d converter 0, input 3. when configured as an adc input, the digital function of the pin must be disabled. o dac_out ? d/a converter output. when configured as the dac output, the digital f unction of the pin must be disabled. i u3_rxd ? receiver input for uart3. p0[27] 50 t1 l3 35 - [8] ii/o p0[27] ? general purpose digital input/output pin. i/o i2c0_sda ? i 2 c0 data input/output. (this pin uses a specialized i2c pad). i/o usb_sda1 ? i2c serial data for communication with an external usb transceiver. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 17 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p0[28] 48 r3 m1 34 - [8] ii/o p0[28] ? general purpose digital input/output pin. i/o i2c0_scl ? i 2 c0 clock input/output (this pin uses a specialized i2c pad. i/o usb_scl1 ? i2c serial clock for communication with an external usb transceiver. p0[29] 61 u4 k5 42 22 [9] ii/o p0[29] ? general purpose digital input/output pin. i/o usb_d+1 ? usb port 1 bidirectional d+ line. i eint0 ? external interrupt 0 input. p0[30] 62 r6 n4 43 23 [9] ii/o p0[30] ? general purpose digital input/output pin. i/o usb_d? 1 ? usb port 1 bidirectional d ? line. i eint1 ? external interrupt 1 input. p0[31] 51 t2 n1 36 - [9] ii/o p0[31] ? general purpose digital input/output pin. i/o usb_d+2 ? usb port 2 bidirectional d+ line. p1[0] to p1[31] i/o port 1: port 1 is a 32 bit i/o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block p1[0] 196 a3 b5 136 76 [3] i; pu i/o p1[0] ? general purpose digital input/output pin. o enet_txd0 ? ethernet transmit data 0 (rmii/mii interface). - r ? function reserved. i t3_cap1 ? capture input for timer 3, channel 1. i/o ssp2_sck ? serial clock for ssp2. p1[1] 194 b5 a5 135 75 [3] i; pu i/o p1[1] ? general purpose digital input/output pin. o enet_txd1 ? ethernet transmit data 1 (rmii/mii interface). - r ? function reserved. o t3_mat3 ? match output for timer 3, channel 3. i/o ssp2_mosi ? master out slave in for ssp2. p1[2] 185 d9 b7 - - [3] i; pu i/o p1[2] ? general purpose digital input/output pin. o enet_txd2 ? ethernet transmit data 2 (mii interface). o sd_clk ? clock output line for sd card interface. o pwm0[1] ? pulse width modulator 0, output 1. p1[3] 177 a10 a9 - - [3] i; pu i/o p1[3] ? general purpose digital input/output pin. o enet_txd3 ? ethernet transmit data 3 (mii interface). i/o sd_cmd ? command line for sd card interface. o pwm0[2] ? pulse width modulator 0, output 2. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 18 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p1[4] 192 a5 c6 133 74 [3] i; pu i/o p1[4] ? general purpose digital input/output pin. o enet_tx_en ? ethernet transmit data enable (rmii/mii interface). - r ? function reserved. o t3_mat2 ? match output for timer 3, channel 2. i/o ssp2_miso ? master in slave out for ssp2. p1[5] 156 a17 b13 - - [3] i; pu i/o p1[5] ? general purpose digital input/output pin. o enet_tx_er ? ethernet transmit e rror (mii interface). o sd_pwr ? power supply enable for external sd card power supply. o pwm0[3] ? pulse width modulator 0, output 3. - r ? function reserved. i cmp1_in[1] ? comparator 1, input 1. p1[6] 171 b11 b10 - - [3] i; pu i/o p1[6] ? general purpose digital input/output pin. i enet_tx_clk ? ethernet transmit clock (mii interface). i/o sd_dat[0] ? data line 0 for sd card interface. o pwm0[4] ? pulse width modulator 0, output 4. - r ? function reserved. i cmp0_in[3] ? comparator 0, input 3. p1[7] 153 d14 c13 - - [3] i; pu i/o p1[7] ? general purpose digital input/output pin. i enet_col ? ethernet collision de tect (mii interface). i/o sd_dat[1] ? data line 1 for sd card interface. o pwm0[5] ? pulse width modulator 0, output 5. - r ? function reserved. i cmp1_in[0] ? comparator 1, input 0. p1[8] 190 c7 b6 132 73 [3] i; pu i/o p1[8] ? general purpose digital input/output pin. i enet_crs (enet_crs_dv) ? ethernet carrier sense (mii interface) or et hernet carrier sense/data valid (rmii interface). - r ? function reserved. o t3_mat1 ? match output for timer 3, channel 1. i/o ssp2_ssel ? slave select for ssp2. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 19 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p1[9] 188 a6 d7 131 72 [3] i; pu i/o p1[9] ? general purpose digital input/output pin. i enet_rxd0 ? ethernet receive data 0 (rmii/mii interface). - r ? function reserved. o t3_mat0 ? match output for timer 3, channel 0. p1[10] 186 c8 a7 129 71 [3] i; pu i/o p1[10] ? general purpose digital input/output pin. i enet_rxd1 ? ethernet receive data 1 (rmii/mii interface). - r ? function reserved. i t3_cap0 ? capture input for timer 3, channel 0. p1[11] 163 a14 a12 - - [3] i; pu i/o p1[11] ? general purpose digital input/output pin. i enet_rxd2 ? ethernet receive data 2 (mii interface). i/o sd_dat[2] ? data line 2 for sd card interface. o pwm0[6] ? pulse width modulator 0, output 6. p1[12] 157 a16 a14 - - [3] i; pu i/o p1[12] ? general purpose digital input/output pin. i enet_rxd3 ? ethernet receive data (mii interface). i/o sd_dat[3] ? data line 3 for sd card interface. i pwm0_cap0 ? capture input for pwm0, channel 0. - r ? function reserved. o cmp1_out ? comparator 1, output. p1[13] 147 d16 d14 - - [3] i; pu i/o p1[13] ? general purpose digital input/output pin. i enet_rx_dv ? ethernet receive data valid (mii interface). p1[14] 184 a7 d8 128 70 [3] i; pu i/o p1[14] ? general purpose digital input/output pin. i enet_rx_er ? ethernet receive error (rmii/mii interface). - r ? function reserved. i t2_cap0 ? capture input for timer 2, channel 0. - r ? function reserved. i cmp0_in[0] ? comparator 0, input 0. p1[15] 182 a8 a8 126 69 [3] i; pu i/o p1[15] ? general purpose digital input/output pin. i enet_rx_clk (enet_ref_clk) ? ethernet receive clock (mii interface) or ethernet reference clock (rmii interface). - r ? function reserved. i/o i2c2_sda ? i 2 c2 data input/output (this pin does not use a specialized i2c pad). table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 20 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p1[16] 180 d10 b8 125 - [3] i; pu i/o p1[16] ? general purpose digital input/output pin. o enet_mdc ? ethernet miim clock. o i2s_tx_mclk ? i2s transmit master clock. - r ? function reserved. - r ? function reserved. i cmp0_in[1] ? comparator 0, input 1. p1[17] 178 a9 c9 123 - [3] i; pu i/o p1[17] ? general purpose digital input/output pin. i/o enet_mdio ? ethernet miim data input and output. o i2s_rx_mclk ? i2s receive master clock. - r ? function reserved. - r ? function reserved. i cmp0_in[2] ? comparator 0, input 2. p1[18] 66 p7 l5 46 25 [3] i; pu i/o p1[18] ? general purpose digital input/output pin. o usb_up_led1 ? it is low when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. it is high when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. it transitions between low and high (flashes) when the host is enabled and detects activity on the bus. o pwm1[1] ? pulse width modulator 1, channel 1 output. i t1_cap0 ? capture input for timer 1, channel 0. - r ? function reserved. i/o ssp1_miso ? master in slave out for ssp1. p1[19] 68 u6 p5 47 26 [3] i; pu i/o p1[19] ? general purpose digital input/output pin. o usb_tx_e1 ? transmit enable signal for usb port 1 (otg transceiver). o usb_ppwr1 ? port power enable signal for usb port 1. i t1_cap1 ? capture input for timer 1, channel 1. o mc_0a ? motor control pwm channel 0, output a. i/o ssp1_sck ? serial clock for ssp1. o u2_oe ? rs-485/eia-485 output enable signal for uart2. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 21 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p1[20] 70 u7 k6 49 27 [3] i; pu i/o p1[20] ? general purpose digital input/output pin. o usb_tx_dp1 ? d+ transmit data for usb port 1 (otg transceiver). o pwm1[2] ? pulse width modulator 1, channel 2 output. i qei_pha ? quadrature encoder interface pha input. i mc_fb0 ? motor control pwm channel 0 feedback input. i/o ssp0_sck ? serial clock for ssp0. o lcd_vd[6] ? lcd data. o lcd_vd[10] ? lcd data. p1[21] 72 r8 n6 50 - [3] i; pu i/o p1[21] ? general purpose digital input/output pin. o usb_tx_dm1 ? d ? transmit data for usb port 1 (otg transceiver). o pwm1[3] ? pulse width modulator 1, channel 3 output. i/o ssp0_ssel ? slave select for ssp0. i mc_abort ? motor control pwm, active low fast abort. - r ? function reserved. o lcd_vd[7] ? lcd data. o lcd_vd[11] ? lcd data. p1[22] 74 u8 m6 51 28 [3] i; pu i/o p1[22] ? general purpose digital input/output pin. i usb_rcv1 ? differential receive data for usb port 1 (otg transceiver). i usb_pwrd1 ? power status for usb port 1 (host power switch). o t1_mat0 ? match output for timer 1, channel 0. o mc_0b ? motor control pwm channel 0, output b. i/o ssp1_mosi ? master out slave in for ssp1. o lcd_vd[8] ? lcd data. o lcd_vd[12] ? lcd data. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 22 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p1[23] 76 p9 n7 53 29 [3] i; pu i/o p1[23] ? general purpose digital input/output pin. i usb_rx_dp1 ? d+ receive data for usb port 1 (otg transceiver). o pwm1[4] ? pulse width modulator 1, channel 4 output. i qei_phb ? quadrature encoder interface phb input. i mc_fb1 ? motor control pwm channel 1 feedback input. i/o ssp0_miso ? master in slave out for ssp0. o lcd_vd[9] ? lcd data. o lcd_vd[13] ? lcd data. p1[24] 78 t9 p7 54 30 [3] i; pu i/o p1[24] ? general purpose digital input/output pin. i usb_rx_dm1 ? d ? receive data for usb port 1 (otg transceiver). o pwm1[5] ? pulse width modulator 1, channel 5 output. i qei_idx ? quadrature encoder interface index input. i mc_fb2 ? motor control pwm channel 2 feedback input. i/o ssp0_mosi ? master out slave in for ssp0. o lcd_vd[10] ? lcd data. o lcd_vd[14] ? lcd data. p1[25] 80 t10 l7 56 31 [3] i; pu i/o p1[25] ? general purpose digital input/output pin. o usb_ls1 ? low speed status for usb port 1 (otg transceiver). o usb_hsten1 ? host enabled status for usb port 1. o t1_mat1 ? match output for timer 1, channel 1. o mc_1a ? motor control pwm channel 1, output a. o clkout ? selectable clock output. o lcd_vd[11] ? lcd data. o lcd_vd[15] ? lcd data. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 23 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p1[26] 82 r10 p8 57 32 [3] i; pu i/o p1[26] ? general purpose digital input/output pin. o usb_sspnd1 ? usb port 1 bus suspend status (otg transceiver). o pwm1[6] ? pulse width modulator 1, channel 6 output. i t0_cap0 ? capture input for timer 0, channel 0. o mc_1b ? motor control pwm channel 1, output b. i/o ssp1_ssel ? slave select for ssp1. o lcd_vd[12] ? lcd data. o lcd_vd[20] ? lcd data. p1[27] 88 t12 m9 61 - [3] i; pu i/o p1[27] ? general purpose digital input/output pin. i usb_int1 ? usb port 1 otg transceiver interrupt (otg transceiver). i usb_ovrcr1 ? usb port 1 over-current status. i t0_cap1 ? capture input for timer 0, channel 1. o clkout ? selectable clock output. - r ? function reserved. o lcd_vd[13] ? lcd data. o lcd_vd[21] ? lcd data. p1[28] 90 t13 p10 63 35 [3] i; pu i/o p1[28] ? general purpose digital input/output pin. i/o usb_scl1 ? usb port 1 i 2 c serial clock (otg transceiver). i pwm1_cap0 ? capture input for pwm1, channel 0. o t0_mat0 ? match output for timer 0, channel 0. o mc_2a ? motor control pwm channel 2, output a. i/o ssp0_ssel ? slave select for ssp0. o lcd_vd[14] ? lcd data. o lcd_vd[22] ? lcd data. p1[29] 92 u14 n10 64 36 [3] i; pu i/o p1[29] ? general purpose digital input/output pin. i/o usb_sda1 ? usb port 1 i 2 c serial data (otg transceiver). i pwm1_cap1 ? capture input for pwm1, channel 1. o t0_mat1 ? match output for timer 0, channel 1. o mc_2b ? motor control pwm channel 2, output b. o u4_txd ? transmitter output for usart4 (input/output in smart card mode). o lcd_vd[15] ? lcd data. o lcd_vd[23] ? lcd data. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 24 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p1[30] 42 p2 k3 30 18 [5] i; pu i/o p1[30] ? general purpose digital input/output pin. i usb_pwrd2 ? power status for usb port 2. i usb_vbus ? monitors the presence of usb bus power. this signal must be high for usb reset to occur. i adc0_in[4] ? a/d converter 0, input 4. when configured as an adc input, the digital function of the pin must be disabled. i/o i2c0_sda ? i 2 c0 data input/output (this pin does not use a specialized i2c pad. o u3_oe ? rs-485/eia-485 output enable signal for uart3. p1[31] 40 p1 k2 28 17 [5] i; pu i/o p1[31] ? general purpose digital input/output pin. i usb_ovrcr2 ? over-current status for usb port 2. i/o ssp1_sck ? serial clock for ssp1. i adc0_in[5] ? a/d converter 0, input 5. when configured as an adc input, the digital function of the pin must be disabled. i/o i2c0_scl ? i 2 c0 clock input/output (this pin does not use a specialized i2c pad. p2[0] to p2[31] i/o port 2: port 2 is a 32 bit i/o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block. p2[0] 154 b17 d12 107 60 [3] i; pu i/o p2[0] ? general purpose digital input/output pin. o pwm1[1] ? pulse width modulator 1, channel 1 output. o u1_txd ? transmitter output for uart1. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. o lcd_pwr ? lcd panel power enable. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 25 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p2[1] 152 e14 c14 106 59 [3] i; pu i/o p2[1] ? general purpose digital input/output pin. o pwm1[2] ? pulse width modulator 1, channel 2 output. i u1_rxd ? receiver input for uart1. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. o lcd_le ? line end signal. p2[2] 150 d15 e11 105 58 [3] i; pu i/o p2[2] ? general purpose digital input/output pin. o pwm1[3] ? pulse width modulator 1, channel 3 output. i u1_cts ? clear to send input for uart1. o t2_mat3 ? match output for timer 2, channel 3. - r ? function reserved. o tracedata[3] ? trace data, bit 3. - r ? function reserved. o lcd_dclk ? lcd panel clock. p2[3] 144 e16 e13 100 55 [3] i; pu i/o p2[3] ? general purpose digital input/output pin. o pwm1[4] ? pulse width modulator 1, channel 4 output. i u1_dcd ? data carrier detect input for uart1. o t2_mat2 ? match output for timer 2, channel 2. - r ? function reserved. o tracedata[2] ? trace data, bit 2. - r ? function reserved. o lcd_fp ? frame pulse (stn). vertical synchronization pulse (tft). p2[4] 142 d17 e14 99 54 [3] i; pu i/o p2[4] ? general purpose digital input/output pin. o pwm1[5] ? pulse width modulator 1, channel 5 output. i u1_dsr ? data set ready input for uart1. o t2_mat1 ? match output for timer 2, channel 1. - r ? function reserved. o tracedata[1] ? trace data, bit 1. - r ? function reserved. o lcd_enab_m ? stn ac bias drive or tft data enable output. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 26 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p2[5] 140 f16 f12 97 53 [3] i; pu i/o p2[5] ? general purpose digital input/output pin. o pwm1[6] ? pulse width modulator 1, channel 6 output. o u1_dtr ? data terminal ready output for uart1. can also be configured to be an rs-485/eia-485 output enable signal for uart1. o t2_mat0 ? match output for timer 2, channel 0. - r ? function reserved. o tracedata[0] ? trace data, bit 0. - r ? function reserved. o lcd_lp ? line synchronization pulse (stn). horizontal synchronization pulse (tft). p2[6] 138 e17 f13 96 52 [3] i; pu i/o p2[6] ? general purpose digital input/output pin. i pwm1_cap0 ? capture input for pwm1, channel 0. i u1_ri ? ring indicator input for uart1. i t2_cap0 ? capture input for timer 2, channel 0. o u2_oe ? rs-485/eia-485 output enable signal for uart2. o traceclk ? trace clock. o lcd_vd[0] ? lcd data. o lcd_vd[4] ? lcd data. p2[7] 136 g16 g11 95 51 [3] i; pu i/o p2[7] ? general purpose digital input/output pin. i can_rd2 ? can2 receiver input. o u1_rts ? request to send output for uart1. can also be configured to be an rs-485 /eia-485 output enable signal for uart1. - r ? function reserved. - r ? function reserved. o spifi_cs ? chip select output for spifi. o lcd_vd[1] ? lcd data. o lcd_vd[5] ? lcd data. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 27 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p2[8] 134 h15 g14 93 50 [3] i; pu i/o p2[8] ? general purpose digital input/output pin. o can_td2 ? can2 transmitter output. o u2_txd ? transmitter output for uart2. i u1_cts ? clear to send input for uart1. o enet_mdc ? ethernet miim clock. - r ? function reserved. o lcd_vd[2] ? lcd data. o lcd_vd[6] ? lcd data. p2[9] 132 h16 h11 92 49 [3] i; pu i/o p2[9] ? general purpose digital input/output pin. o usb_connect1 ? usb1 softconnect control. signal used to switch an external 1.5 k ? resistor under the software control. used with the softconnect usb feature. i u2_rxd ? receiver input for uart2. i u4_rxd ? receiver input for usart4. i/o enet_mdio ? ethernet miim data input and output. - r ? function reserved. i lcd_vd[3] ? lcd data. i lcd_vd[7] ? lcd data. p2[10] 110 n15 m13 76 41 [10] i; pu i/o p2[10] ? general purpose digital input/output pin. this pin includes a 5 ns input glitch filter. a low on this pin while reset is low forces the on-chip boot loader to take over control of the part after a reset and go into isp mode. i eint0 ? external interrupt 0 input. i nmi ? non-maskable interrupt input. p2[11] 108 t17 m12 75 - [10] i; pu i/o p2[11] ? general purpose digital input/output pin. this pin includes a 5 ns input glitch filter. i eint1 ? external interrupt 1 input. i/o sd_dat[1] ? data line 1 for sd card interface. i/o i2s_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . - r ? function reserved. - r ? function reserved. - r ? function reserved. o lcd_clkin ? lcd clock. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 28 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p2[12] 106 n14 n14 73 - [10] i; pu i/o p2[12] ? general purpose digital input/output pin. this pin includes a 5 ns input glitch filter. i eint2 ? external interrupt 2 input. i/o sd_dat[2] ? data line 2 for sd card interface. i/o i2s_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . o lcd_vd[4] ? lcd data. o lcd_vd[3] ? lcd data. o lcd_vd[8] ? lcd data. o lcd_vd[18] ? lcd data. p2[13] 102 t16 m11 71 - [10] i; pu i/o p2[13] ? general purpose digital input/output pin. this pin includes a 5 ns input glitch filter. i eint3 ? external interrupt 3 input. i/o sd_dat[3] ? data line 3 for sd card interface. i/o i2s_tx_sda ? transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . - r ? function reserved. o lcd_vd[5] ? lcd data. o lcd_vd[9] ? lcd data. o lcd_vd[19] ? lcd data. p2[14] 91 r12 - - - [3] i; pu i/o p2[14] ? general purpose digital input/output pin. o emc_cs2 ? low active chip select 2 signal. i/o i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i2c pad). i t2_cap0 ? capture input for timer 2, channel 0. p2[15] 99 p13 - - - [3] i; pu i/o p2[15] ? general purpose digital input/output pin. o emc_cs3 ? low active chip select 3 signal. i/o i2c1_scl ? i 2 c1 clock input/output (this pin does not use a specialized i2c pad). i t2_cap1 ? capture input for timer 2, channel 1. p2[16] 87 r11 p9 - - [3] i; pu i/o p2[16] ? general purpose digital input/output pin. o emc_cas ? low active sdram column address strobe. p2[17] 95 r13 p11 - - [3] i; pu i/o p2[17] ? general purpose digital input/output pin. o emc_ras ? low active sdram row address strobe. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 29 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p2[18] 59 u3 p3 - - [6] i; pu i/o p2[18] ? general purpose digital input/output pin. o emc_clk[0] ? sdram clock 0. p2[19] 67 r7 n5 - - [6] i; pu i/o p2[19] ? general purpose digital input/output pin. o emc_clk[1] ? sdram clock 1. p2[20] 73 t8 p6 - - [3] i; pu i/o p2[20] ? general purpose digital input/output pin. o emc_dycs0 ? sdram chip select 0. p2[21] 81 u11 n8 - - [3] i; pu i/o p2[21] ? general purpose digital input/output pin. o emc_dycs1 ? sdram chip select 1. p2[22] 85 u12 - - - [3] i; pu i/o p2[22] ? general purpose digital input/output pin. o emc_dycs2 ? sdram chip select 2. i/o ssp0_sck ? serial clock for ssp0. i t3_cap0 ? capture input for timer 3, channel 0. p2[23] 64 u5 - - - [3] i; pu i/o p2[23] ? general purpose digital input/output pin. o emc_dycs3 ? sdram chip select 3. i/o ssp0_ssel ? slave select for ssp0. i t3_cap1 ? capture input for timer 3, channel 1. p2[24] 53 p5 p1 - - [3] i; pu i/o p2[24] ? general purpose digital input/output pin. o emc_cke0 ? sdram clock enable 0. p2[25] 54 r4 p2 - - [3] i; pu i/o p2[25] ? general purpose digital input/output pin. o emc_cke1 ? sdram clock enable 1. p2[26] 57 t4 - - - [3] i; pu i/o p2[26] ? general purpose digital input/output pin. o emc_cke2 ? sdram clock enable 2. i/o ssp0_miso ? master in slave out for ssp0. o t3_mat0 ? match output for timer 3, channel 0. p2[27] 47 p3 - - - [3] i; pu i/o p2[27] ? general purpose digital input/output pin. o emc_cke3 ? sdram clock enable 3. i/o ssp0_mosi ? master out slave in for ssp0. o t3_mat1 ? match output for timer 3, channel 1. p2[28] 49 p4 m2 - - [3] i; pu i/o p2[28] ? general purpose digital input/output pin. o emc_dqm0 ? data mask 0 used with sdram and static devices. p2[29] 43 n3 l1 - - [3] i; pu i/o p2[29] ? general purpose digital input/output pin. o emc_dqm1 ? data mask 1 used with sdram and static devices. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 30 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p2[30] 31 l4 - - 12 [3] i; pu i/o p2[30] ? general purpose digital input/output pin. o emc_dqm2 ? data mask 2 used with sdram and static devices. i/o i2c2_sda ? i 2 c2 data input/output (this pin does not use a specialized i2c pad). o t3_mat2 ? match output for timer 3, channel 2. p2[31] 39 n2 - - - [3] i; pu i/o p2[31] ? general purpose digital input/output pin. o emc_dqm3 ? data mask 3 used with sdram and static devices. i/o i2c2_scl ? i 2 c2 clock input/output (this pin does not use a specialized i2c pad). o t3_mat3 ? match output for timer 3, channel 3. p3[0] to p3[31] i/o port 3: port 3 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 3 pins depends upon the pin function selected via the pin connect block. p3[0] 197 b4 d6 137 - [3] i; pu i/o p3[0] ? general purpose digital input/output pin. i/o emc_d[0] ? external memory data line 0. p3[1] 201 b3 e6 140 - [3] i; pu i/o p3[1] ? general purpose digital input/output pin. i/o emc_d[1] ? external memory data line 1. p3[2] 207 b1 a2 144 - [3] i; pu i/o p3[2] ? general purpose digital input/output pin. i/o emc_d[2] ? external memory data line 2. p3[3] 3 e4 g5 2 - [3] i; pu i/o p3[3] ? general purpose digital input/output pin. i/o emc_d[3] ? external memory data line 3. p3[4] 13 f2 d3 9 - [3] i; pu i/o p3[4] ? general purpose digital input/output pin. i/o emc_d[4] ? external memory data line 4. p3[5] 17g1e3 12- [3] i; pu i/o p3[5] ? general purpose digital input/output pin. i/o emc_d[5] ? external memory data line 5. p3[6] 23j1 f4 16- [3] i; pu i/o p3[6] ? general purpose digital input/output pin. i/o emc_d[6] ? external memory data line 6. p3[7] 27l1 g319- [3] i; pu i/o p3[7] ? general purpose digital input/output pin. i/o emc_d[7] ? external memory data line 7. p3[8] 191 d8 a6 - - [3] i; pu i/o p3[8] ? general purpose digital input/output pin. i/o emc_d[8] ? external memory data line 8. p3[9] 199 c5 a4 - - [3] i; pu i/o p3[9] ? general purpose digital input/output pin. i/o emc_d[9] ? external memory data line 9. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 31 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p3[10] 205 b2 b3 - - [3] i; pu i/o p3[10] ? general purpose digital input/output pin. i/o emc_d[10] ? external memory data line 10. p3[11] 208 d5 b2 - - [3] i; pu i/o p3[11] ? general purpose digital input/output pin. i/o emc_d[11] ? external memory data line 11. p3[12] 1 d4 a1 - - [3] i; pu i/o p3[12] ? general purpose digital input/output pin. i/o emc_d[12] ? external memory data line 12. p3[13] 7 c1 c1 - - [3] i; pu i/o p3[13] ? general purpose digital input/output pin. i/o emc_d[13] ? external memory data line 13. p3[14] 21 h2 f1 - - [3] i; pu i/o p3[14] ? general purpose digital input/output pin. i/o emc_d[14] ? external memory data line 14. p3[15] 28 m1 g4 - - [3] i; pu i/o p3[15] ? general purpose digital input/output pin. i/o emc_d[15] ? external memory data line 15. p3[16] 137 f17 - - - [3] i; pu i/o p3[16] ? general purpose digital input/output pin. i/o emc_d[16] ? external memory data line 16. o pwm0[1] ? pulse width modulator 0, output 1. o u1_txd ? transmitter output for uart1. p3[17] 143 f15 - - - [3] i; pu i/o p3[17] ? general purpose digital input/output pin. i/o emc_d[17] ? external memory data line 17. o pwm0[2] ? pulse width modulator 0, output 2. i u1_rxd ? receiver input for uart1. p3[18] 151 c15 - - - [3] i; pu i/o p3[18] ? general purpose digital input/output pin. i/o emc_d[18] ? external memory data line 18. o pwm0[3] ? pulse width modulator 0, output 3. i u1_cts ? clear to send input for uart1. p3[19] 161 b14 - - - [3] i; pu i/o p3[19] ? general purpose digital input/output pin. i/o emc_d[19] ? external memory data line 19. o pwm0[4] ? pulse width modulator 0, output 4. i u1_dcd ? data carrier detect input for uart1. p3[20] 167 a13 - - - [3] i; pu i/o p3[20] ? general purpose digital input/output pin. i/o emc_d[20] ? external memory data line 20. o pwm0[5] ? pulse width modulator 0, output 5. i u1_dsr ? data set ready input for uart1. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 32 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p3[21] 175 c10 - - - [3] i; pu i/o p3[21] ? general purpose digital input/output pin. i/o emc_d[21] ? external memory data line 21. o pwm0[6] ? pulse width modulator 0, output 6. o u1_dtr ? data terminal ready output for uart1. can also be configured to be an rs-485/eia-485 output enable signal for uart1. p3[22] 195 c6 - - -- [3] i; pu i/o p3[22] ? general purpose digital input/output pin. i/o emc_d[22] ? external memory data line 22. i pwm0_cap0 ? capture input for pwm0, channel 0. i u1_ri ? ring indicator input for uart1. p3[23] 65 t6 m4 45 - [3] i; pu i/o p3[23] ? general purpose digital input/output pin. i/o emc_d[23] ? external memory data line 23. i pwm1_cap0 ? capture input for pwm1, channel 0. i t0_cap0 ? capture input for timer 0, channel 0. p3[24] 58 r5 n3 40 - [3] i; pu i/o p3[24] ? general purpose digital input/output pin. i/o emc_d[24] ? external memory data line 24. o pwm1[1] ? pulse width modulator 1, output 1. i t0_cap1 ? capture input for timer 0, channel 1. p3[25] 56 u2 m3 39 - [3] i; pu i/o p3[25] ? general purpose digital input/output pin. i/o emc_d[25] ? external memory data line 25. o pwm1[2] ? pulse width modulator 1, output 2. o t0_mat0 ? match output for timer 0, channel 0. p3[26] 55 t3 k7 38 - [3] i; pu i/o p3[26] ? general purpose digital input/output pin. i/o emc_d[26] ? external memory data line 26. o pwm1[3] ? pulse width modulator 1, output 3. o t0_mat1 ? match output for timer 0, channel 1. i stclk ? system tick timer clock input. p3[27] 203 a1 - - - [3] i; pu i/o p3[27] ? general purpose digital input/output pin. i/o emc_d[27] ? external memory data line 27. o pwm1[4] ? pulse width modulator 1, output 4. i t1_cap0 ? capture input for timer 1, channel 0. p3[28] 5 d2 - - - [3] i; pu i/o p3[28] ? general purpose digital input/output pin. i/o emc_d[28] ? external memory data line 28. o pwm1[5] ? pulse width modulator 1, output 5. i t1_cap1 ? capture input for timer 1, channel 1. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 33 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p3[29] 11 f3 - - - [3] i; pu i/o p3[29] ? general purpose digital input/output pin. i/o emc_d[29] ? external memory data line 29. o pwm1[6] ? pulse width modulator 1, output 6. o t1_mat0 ? match output for timer 1, channel 0. p3[30] 19 h3 - - - [3] i; pu i/o p3[30] ? general purpose digital input/output pin. i/o emc_d[30] ? external memory data line 30. o u1_rts ? request to send output for uart1. can also be configured to be an rs-485 /eia-485 output enable signal for uart1. o t1_mat1 ? match output for timer 1, channel 1. p3[31] 25 j3 - - - [3] i; pu i/o p3[31] ? general purpose digital input/output pin. i/o emc_d[31] ? external memory data line 31. - r ? function reserved. o t1_mat2 ? match output for timer 1, channel 2. p4[0] to p4[31] i/o port 4: port 4 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 4 pins depends upon the pin function selected via the pin connect block. p4[0] 75u9 l6 52- [3] i; pu i/o p4[0] ? general purpose digital input/output pin. i/o emc_a[0] ? external memory address line 0. p4[1] 79 u10 m7 55 - [3] i; pu i/o p4[1] ? general purpose digital input/output pin. i/o emc_a[1] ? external memory address line 1. p4[2] 83 t11 m8 58 - [3] i; pu i/o p4[2] ? general purpose digital input/output pin. i/o emc_a[2] ? external memory address line 2. p4[3] 97 u16 k9 68 - [3] i; pu i/o p4[3] ? general purpose digital input/output pin. i/o emc_a[3] ? external memory address line 3. p4[4] 103 r15 p13 72 - [3] i; pu i/o p4[4] ? general purpose digital input/output pin. i/o emc_a[4] ? external memory address line 4. p4[5] 107 r16 h10 74 - [3] i; pu i/o p4[5] ? general purpose digital input/output pin. i/o emc_a[5] ? external memory address line 5. p4[6] 113 m14 k10 78 - [3] i; pu i/o p4[6] ? general purpose digital input/output pin. i/o emc_a[6] ? external memory address line 6. p4[7] 121 l16 k12 84 - [3] i; pu i/o p4[7] ? general purpose digital input/output pin. i/o emc_a[7] ? external memory address line 7. p4[8] 127 j17 j11 88 - [3] i; pu i/o p4[8] ? general purpose digital input/output pin. i/o emc_a[8] ? external memory address line 8. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 34 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p4[9] 131 h17 h12 91 - [3] i; pu i/o p4[9] ? general purpose digital input/output pin. i/o emc_a[9] ? external memory address line 9. p4[10] 135 g17 g12 94 - [3] i; pu i/o p4[10] ? general purpose digital input/output pin. i/o emc_a[10] ? external memory address line 10. p4[11] 145 f14 f11 101 - [3] i; pu i/o p4[11] ? general purpose digital input/output pin. i/o emc_a[11] ? external memory address line 11. p4[12] 149 c16 f10 104 - [3] i; pu i/o p4[12] ? general purpose digital input/output pin. i/o emc_a[12] ? external memory address line 12. p4[13] 155 b16 b14 108 - [3] i; pu i/o p4[13] ? general purpose digital input/output pin. i/o emc_a[13] ? external memory address line 13. p4[14] 159 b15 e8 110 - [3] i; pu i/o p4[14] ? general purpose digital input/output pin. i/o emc_a[14] ? external memory address line 14. p4[15] 173 a11 c10 120 - [3] i; pu i/o p4[15] ? general purpose digital input/output pin. i/o emc_a[15] ? external memory address line 15. p4[16] 101 u17 n12 - - [3] i; pu i/o p4[16] ? general purpose digital input/output pin. i/o emc_a[16] ? external memory address line 16. p4[17] 104 p14 n13 - - [3] i; pu i/o p4[17] ? general purpose digital input/output pin. i/o emc_a[17] ? external memory address line 17. p4[18] 105 p15 p14 - - [3] i; pu i/o p4[18] ? general purpose digital input/output pin. i/o emc_a[18] ? external memory address line 18. p4[19] 111 p16 m14 - - [3] i; pu i/o p4[19] ? general purpose digital input/output pin. i/o emc_a[19] ? external memory address line 19. p4[20] 109 r17 - - - [3] i; pu i/o p4[20] ? general purpose digital input/output pin. i/o emc_a[20] ? external memory address line 20. i/o i2c2_sda ? i 2 c2 data input/output (this pin does not use a specialized i2c pad). i/o ssp1_sck ? serial clock for ssp1. p4[21] 115 m15 - - - [3] i; pu i/o p4[21] ? general purpose digital input/output pin. i/o emc_a[21] ? external memory address line 21. i/o i2c2_scl ? i 2 c2 clock input/output (this pin does not use a specialized i2c pad). i/o ssp1_ssel ? slave select for ssp1. p4[22] 123 k14 - - - [3] i; pu i/o p4[22] ? general purpose digital input/output pin. i/o emc_a[22] ? external memory address line 22. o u2_txd ? transmitter output for uart2. i/o ssp1_miso ? master in slave out for ssp1. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 35 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p4[23] 129 j15 - - - [3] i; pu i/o p4[23] ? general purpose digital input/output pin. i/o emc_a[23] ? external memory address line 23. i u2_rxd ? receiver input for uart2. i/o ssp1_mosi ? master out slave in for ssp1. p4[24] 183 b8 c8 127 -- [3] i; pu i/o p4[24] ? general purpose digital input/output pin. o emc_oe ? low active output enable signal. p4[25] 179 b9 d9 124 - [3] i; pu i/o p4[25] ? general purpose digital input/output pin. o emc_we ? low active write enable signal. p4[26] 119 l15 k13 - - [3] i; pu i/o p4[26] ? general purpose digital input/output pin. o emc_bls0 ? low active byte lane select signal 0. p4[27] 139 g15 f14 - - [3] i; pu i/o p4[27] ? general purpose digital input/output pin. o emc_bls1 ? low active byte lane select signal 1. p4[28] 170 c11 d10 118 65 [3] i; pu i/o p4 [28] ? general purpose digital input/output pin. o emc_bls2 ? low active byte lane select signal 2. o u3_txd ? transmitter output for uart3. o t2_mat0 ? match output for timer 2, channel 0. - r ? function reserved. o lcd_vd[6] ? lcd data. o lcd_vd[10] ? lcd data. o lcd_vd[2] ? lcd data. p4[29] 176 b10 b9 122 68 [3] i; pu i/o p4[29] ? general purpose digital input/output pin. o emc_bls3 ? low active byte lane select signal 3. i u3_rxd ? receiver input for uart3. o t2_mat1 ? match output for timer 2, channel 1. i/o i2c2_scl ? i 2 c2 clock input/output (this pin does not use a specialized i2c pad). o lcd_vd[7] ? lcd data. o lcd_vd[11] ? lcd data. o lcd_vd[3] ? lcd data. p4[30] 187 b7 c7 130 - [3] i; pu i/o p4[30] ? general purpose digital input/output pin. o emc_cs0 ? low active chip select 0 signal. - r ? function reserved. - r ? function reserved. - r ? function reserved. o cmp0_out ? comparator 0, output. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 36 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller p4[31] 193 a4 e7 134 - [3] i; pu i/o p4[31] ? general purpose digital input/output pin. o emc_cs1 ? low active chip select 1 signal. p5[0] to p5[4] i/o port 5: port 5 is a 5-bit i/o port with individual direction controls for each bit. the operation of port 5 pins depends upon the pin function selected via the pin connect block. p5[0] 9 f4 e5 6 - [3] i; pu i/o p5[0] ? general purpose digital input/output pin. i/o emc_a[24] ? external memory address line 24. i/o ssp2_mosi ? master out slave in for ssp2. o t2_mat2 ? match output for timer 2, channel 2. p5[1] 30j4 h121- [3] i; pu i/o p5[1] ? general purpose digital input/output pin. i/o emc_a[25] ? external memory address line 25. i/o ssp2_miso ? master in slave out for ssp2. o t2_mat3 ? match output for timer 2, channel 3. p5[2] 117 l14 l12 81 - [11] ii/o p5[2] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o t3_mat2 ? match output for timer 3, channel 2. - r ? function reserved. i/o i2c0_sda ? i 2 c0 data input/output (this pin uses a specialized i 2 c pad that supports i 2 c fast mode plus). p5[3] 141 g14 g10 98 - [11] ii/o p5[3] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. i u4_rxd ? receiver input for usart4. i/o i2c0_scl ? i 2 c0 clock input/output (this pin uses a specialized i 2 c pad that supports i 2 c fast mode plus. p5[4] 206 c3 c4 143 - [3] i; pu i/o p5[4] ? general purpose digital input/output pin. o u0_oe ? rs-485/eia-485 output enable signal for uart0. - r ? function reserved. o t3_mat3 ? match output for timer 3, channel 3. o u4_txd ? transmitter output for usart4 (input/output in smart card mode). jtag_tdo (swo) 2d3b111 [3] o test data out for jtag interf ace. also used as serial wire trace output. jtag_tdi 4 c2 c3 3 2 [3] i test data in for jtag interface. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 37 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller jtag_tms (swdio) 6e3c243 [3] i test mode select for jtag interface. also used as serial wire debug data input/output. jtag_trst 8d1d454 [3] i test reset for jtag interface. jtag_tck (swdclk) 10 e2 d2 7 5 [3] i test clock for jtag interface. this clock must be slower than 1 /6 of the cpu clock (cclk) for the jtag interface to operate. also used as serial wire clock. reset 35 m2 j1 24 14 [12] i external reset input. a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. this pin includes a 20 ns input glitch filter. rstout 29 k3 h2 20 11 [3] o reset status output. a low ou tput on this pin indicates that the device is in the reset state for any reason. this reflects the reset input pi n and all internal reset sources. rtc_alarm 37 n1 h5 26 - [13] o rtc controlled output. this is a 1.8 v pin. it goes high when a rtc alarm is generated. rtcx1 34k2 j2 2313 [14] [15] i input to the rtc 32 khz ultra-low power oscillator circuit. rtcx2 36l2 j3 2515 [14] [15] o output from the rtc 32 khz ultra-low power oscillator circuit. usb_d ? 2 52u1 n237- [9] i/o usb port 2 bidirectional d ? line. vbat 38 m3 k1 27 16 i rtc power supply: 3.3 v on this pin supplies power to the rtc. v dd(reg)(3v3) 26, 86, 174 h4, p11, d11 g1, n9, e9 18, 60, 121 34, 67 s 3.3 v regulator supply voltage: this is the power supply for the on-chip voltage regulator that supplies internal logic. v dda 20 g4 f2 14 8 s analog 3.3 v pad supply vo ltage: this can be connected to the same supply as v dd(3v3) but should be isolated to minimize noise and error. this voltage is used to power the adc and dac. tie this pin to 3.3 v if the adc and dac are not used. v dd(3v3) 15, 60, 71, 89, 112, 125, 146, 165, 181, 198 g3, p6, p8, u13, p17, k16, c17, b13, c9, d7 e2, l4, k8, l11, j14, e12, e10, c5 41, 62, 77, 102, 114, 138 21, 42, 56, 77 s 3.3 v supply voltage: this is the power supply voltage for i/o other than pins in the vbat domain. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 38 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [1] pu = internal pull-up enabled (for v dd(reg)(3v3) = 3.3 v, pulled up to 3.3 v); ia = inactive , no pull-up/down enabled; f = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. [2] i = input; o = output; g = ground; s = supply. [3] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis. [4] 5 v tolerant standard pad (5 v tolerant if v dd(3v3) present; if v dd(3v3) not present, do not exceed 3.6 v) pr oviding digital i/o functions with ttl levels and hysteresis. this pad can be powered by vbat. [5] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis and analog input. when configured as a adc i nput, digital section of the pad is disabled. [6] 5 v tolerant fast pad (5 v tolerant if v dd(3v3) present; if v dd(3v3) not present, do not exceed 3.6 v) prov iding digital i/o functions with ttl levels and hysteresis. [7] 5 v tolerant pad providing digital i/o with ttl levels and hysteresis and analog output functi on. when configured as the dac output, digital section of the pad is disabled. [8] open-drain 5 v tolerant digital i/o pad, compatible with i 2 c-bus 400 khz specification. it requires an external pull-up to provide output functionality. when power is switch ed off, this pin connected to the i 2 c-bus is floating and does not disturb the i 2 c lines. open-drain configuration applies to al l functions on this pin. [9] not 5 v tolerant. pad provides digital i/o and usb functions. it is designed in accordance with the usb specification, revision 2.0 (full-speed and low-speed mode only). [10] 5 v tolerant pad with 5 ns glitch filter providin g digital i/o functions with ttl levels and hysteresis. vrefp 24 k1 g2 17 10 s adc positive reference voltage: this should be the same voltage as v dda , but should be isolated to minimize noise and error. the voltage level on this pin is used as a reference for adc and dac. tie this pin to 3.3 v if the adc and dac are not used. v ss 33, 63, 77, 93, 114, 133, 148, 169, 189, 200 l3, t5, r9, p12, n16, h14, e15, a12, b6, a2 h4, p4, l9, l13, g13, d13, c11, b4 44, 65, 79, 103, 117, 139 24, 43, 57, 78 g ground: 0 v reference for digital io pins. v ssreg 32, 84, 172 d12, k4, p10 h3, l8, a10 22, 59, 119 33, 66 g ground: 0 v reference for internal logic. v ssa 22 j2 f3 15 9 g analog ground: 0 v power supply and reference for the adc and dac. this should be the same voltage as v ss , but should be isolated to minimize noise and error. xtal1 44 m4 l2 31 19 [14] [16] i input to the oscillator circuit and internal clock generator circuits. xtal2 46 n4 k4 33 20 [14] [16] o output from the oscillator amplifier. table 3. pin description ?continued not all functions are available on all parts. see table 2 (ethernet, usb, lcd, qei, sd/mmc, comparator pins) and table 5 (emc pins). symbol pin lqfp208 ball tfbga208 ball tfbga180 pin lqfp144 pin lqfp80 reset state [1] type [2] description
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 39 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [11] open-drain 5 v tolerant digital i/o pad, compatible with i 2 c-bus 1 mhz specification. it requires an external pull-up to provide output functionality. when power is switch ed off, this pin connected to the i 2 c-bus is floating and does not disturb the i 2 c lines. open-drain configuration applies to al l functions on this pin. [12] 5 v tolerant pad with 20 ns glitch filter providi ng digital i/o function with ttl levels and hysteresis. [13] this pad can be powered from vbat. [14] pad provides special analog functionality. [15] if the rtc is not used, these pins can be left floating. [16] when the main oscillator is not used, connect xtal1 and xta l2 as follows: xtal1 can be left floating or can be grounded (gr ounding is preferred to reduce susceptibility to noise). xtal2 should be left floating. 7. functional description 7.1 architectural overview the arm cortex-m4 includes th ree ahb-lite buses: the system bus, the i-code bus, and the d-code bus. the i-code and d-code core buses are faster than the system bus and are used similarly to tightly coupled memory (tcm) interfaces: one bus dedicated for instruction fetch (i-code) and one bus for data access (d-code). the use of two core buses allows for simultaneous operations if conc urrent operations target different devices. the lpc408x/7x use a multi-layer ahb matrix to connect the arm cortex-m4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slav es ports of the matrix to be accessed simultaneously by different bus masters. 7.2 arm cortex-m4 processor the arm cortex-m4 processor is running at fr equencies of up to 120 mhz. the processor executes the thumb-2 instruction set for optimal performance and code size, including hardware division, single-cycle multiply, and bit-field manipulation. a memory protection unit (mpu) supporting eight regions is included. 7.3 arm cortex-m4 floating point unit (fpu) remark: the fpu is available on parts lp4088/78/76. the fpu supports single-precision floating-po int computation functionality in compliance with the ansi/ieee standard 754- 2008. the fpu pr ovides add, subtrac t, multiply, divide, multiply and accumulate, and square root operations. it also performs a variety of conversions between fixed-point, floa ting-point, and integer data formats. 7.4 on-chip flash program memory the lpc408x/7x contain up to 512 kb of on-chip flash program memory. a new two-port flash accelerator maximizes performance fo r use with the two fast ahb-lite buses. 7.5 eeprom the lpc408x/7x contains up to 4032 byte of on-chip byte-erasable and byte-programmable eeprom data memory.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 40 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 7.6 on-chip sram the lpc408x/7x contain a total of up to 96 kb on-chip sram data memory. this includes 64 kb main sram, accessible by the cpu and dma controller on a higher-speed bus, and up to two additional 16 kb peripheral sram blocks situat ed on a separate slave port on the ahb mult ilayer matrix. this architecture allows cpu and dma accesses to be spread over three separate rams that can be accessed simultaneously. 7.7 memory protection unit (mpu) the lpc408x/7x have a memory protection unit (mpu) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. the mpu allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses th at could potentially break the system. the mpu separates the memory into distinct regions and implements protection by preventing disallowed accesses. the mpu supports up to eight regions each of which can be divided into eight subregions. accesses to memory locations that are not defined in the mpu regions, or not permitted by the region setting, will cause the memo ry management fault exception to take place. 7.8 memory map table 4. lpc408x/7x memory usage and details address range general use address range details and description 0x0000 0000 to 0x1fff ffff on-chip non-volatile memory 0x0000 0000 - 0x0007 ffff for devices with 512 kb of flash memory. 0x0000 0000 - 0x0003 ffff for devices with 256 kb of flash memory. 0x0000 0000 - 0x0001 ffff for devices with 128 kb of flash memory. 0x0000 0000 - 0x0000 ffff for devices with 64 kb of flash memory. on-chip sram 0x1000 0000 - 0x1000 ffff for devices with 64 kb of main sram. 0x1000 0000 - 0x1000 7fff for devices with 32 kb of main sram. 0x1000 0000 - 0x1000 3fff for devices with 16 kb of main sram. boot rom 0x1fff 0000 - 0x1fff 1fff 8 kb boot rom with flash services. 0x2000 0000 to 0x3fff ffff on-chip sram (typically used for peripheral data) 0x2000 0000 - 0x2000 1fff peripheral sram - bank 0 (first 8 kb) 0x2000 2000 - 0x2000 3fff peripheral sram - bank 0 (second 8 kb) 0x2000 4000 - 0x2000 7fff peripheral sram - bank 1 (16 kb) ahb peripherals 0x2008 0000 - 0x200b ffff see figure 7 for details 0x4000 0000 to 0x7fff ffff apb peripherals 0x4000 0000 - 0x4007 ffff apb0 peripherals, up to 32 peripheral blocks of 16 kb each. 0x4008 0000 - 0x400f ffff apb1 peripherals, up to 32 peripheral blocks of 16 kb each.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 41 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller the lpc408x/7x incorporate several distinct memory regions, shown in the following figures. figure 7 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb peripheral area is 2 mb in size, and is divided to allow for up to 128 peripherals. the apb peripheral area is 1 mb in size and is divided to allow for up to 64 peripherals. each peripheral of either type is allocated 16 kb of space. this allows simplifying the address decoding for each peripheral. 0x8000 0000 to 0xdfff ffff off-chip memory via the external memory controller four static memory chip selects: 0x8000 0000 - 0x83ff ffff static memory chip select 0 (up to 64 mb) 0x9000 0000 - 0x93ff ffff static memory chip select 1 (up to 64 mb) 0x9800 0000 - 0x9bff ffff static memory chip select 2 (up to 64 mb) 0x9c00 0000 - 0x9fff ffff static memory chip select 3 (up to 64 mb) four dynamic memory chip selects: 0xa000 0000 - 0xafff ffff dynamic memory chip select 0 (up to 256mb) 0xb000 0000 - 0xbfff ffff dynamic memory chip select 1 (up to 256mb) 0xc000 0000 - 0xcfff ffff dynamic memory chip select 2 (up to 256mb) 0xd000 0000 - 0xdfff ffff dynamic memory chip select 3 (up to 256mb) 0xe000 0000 to 0xe00f ffff cortex-m4 private peripheral bus 0xe000 0000 - 0xe00f ffff cortex-m4 related functions, includes the nvic and system tick timer. table 4. lpc408x/7x memory usage and details address range general use address range details and description
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 42 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller (1) not available on all parts. see ta b l e 2 and ta b l e 4 . fig 7. lpc408x/7x memory map 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4002 c000 0x4003 4000 0x4003 0000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 c000 0x4006 0000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 apb1 peripherals 0x4008 0000 0x4008 8000 0x4008 c000 0x4009 0000 0x4009 4000 0x4009 8000 0x4009 c000 0x400a 0000 0x400a 4000 0x400a 8000 0x400a c000 0x400b 0000 0x400b 4000 0x400b 8000 0x400b c000 0x400c 0000 0x400f c000 0x4010 0000 ssp0 dac timer 2 timer 3 uart2 uart3 usart4 (1) i 2 c2 1 - 0 reserved 2 3 4 5 6 7 8 9 10 ssp2 i 2 s 11 12 reserved motor control pwm reserved 30 - 17 reserved 13 14 15 16 system control 31 reserved emc 4 x static chip select (1) emc 4 x dynamic chip select (1) reserved private peripheral bus 0 gb 0.5 gb 4 gb 1 gb 0x1fff 0000 0x2000 0000 0x2000 8000 0x2008 0000 0x2200 0000 0x200a 0000 0x2400 0000 0x2800 0000 0x4000 0000 0x4008 0000 0x4010 0000 0x4200 0000 0x4400 0000 0x8000 0000 0xa000 0000 0xe000 0000 0xe010 0000 0xffff ffff reserved reserved reserved spifi data reserved reserved apb0 peripherals 0xe004 0000 ahb peripherals apb1 peripherals peripheral sram bit-band alias addressing peripheral bit-band alias addressing 0x2000 4000 0x2000 2000 lpc408x/7x qei (1) sd/mmc (1) apb0 peripherals wwdt timer 0 timer 1 uart0 uart1 reserved reserved can af ram can common can1 can2 can af registers pwm0 i 2 c0 rtc/event recorder + backup registers gpio interrupts pin connect ssp1 adc 22 - 19 reserved i 2 c1 31 - 24 reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 pwm1 8 kb boot rom 0x0000 0000 0x0000 0400 active interrupt vectors + 256 words i-code/d-code memory space 002aag736 reserved 0x1fff 2000 0x2900 0000 reserved reserved 0x2008 0000 0x2008 4000 0x2008 8000 0x2008 c000 0x200a 0000 0x2009 c000 ahb peripherals lcd (1) usb (1) ethernet (1) gpdma controller 0 1 2 3 0x2009 0000 crc engine 4 0x2009 4000 5 0x2009 8000 gpio emc registers 6 7 0x0000 0000 0x0001 0000 0x0002 0000 0x0004 0000 0x0008 0000 0x1000 0000 0x1000 4000 0x1000 8000 0x1001 0000 64 kb on- chip flash (lpc4072) 128 kb on- chip flash (lpc4074) 256 kb on-chip flash (lpc4076) 512 kb on-chip flash (lpc4078) reserved 16 kb main sram (lpc4072) 32 kb main sram (lpc4074) 64 kb main sram (lpc4088/78/76) 16 kb peripheral sram1 (lpc4088/78) 8 kb peripheral sram0 (lpc4074/72) 16 kb peripheral sram0 (lpc4088/78/76)
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 43 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 7.9 nested vectored inte rrupt controller (nvic) the nvic is an integral part of the cortex-m 4. the tight coupling to the cpu allows for low interrupt latency and efficient processing of late arriving interrupts. 7.9.1 features ? controls system exceptions and peripheral interrupts. ? on the lpc408x/7x, the nvic supports 40 vectored interrupts. ? 32 programmable interrupt priority levels , with hardware prio rity level masking. ? relocatable vector table. ? non-maskable interrupt (nmi). ? software interr upt generation. 7.9.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. any pin on port 0 and port 2 regardless of the selected function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. 7.10 pin connect block the pin connect block allows selected pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupts being enabled. activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. most pins can also be configured as open-drai n outputs or to have a pull-up, pull-down, or no resistor enabled. 7.11 external memory controller (emc) remark: the emc is available for parts lpc4088/78/76. supported memory size and type and emc bus width vary for different packages (see ta b l e 2 ). the emc pin configuration for each part is shown in ta b l e 5 .
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 44 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller the lpc408x/7x emc is an arm primecell multiport memory controller peripheral offering support for a synchronous static memory devices such as ram, rom, and flash. in addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. the emc is an advanced microc ontroller bus architecture (amba) compliant peripheral. 7.11.1 features ? dynamic memory interface support in cluding single data rate sdram. ? asynchronous static memory device suppor t including ram, rom, and flash, with or without asynchronous page mode. ? low transaction latency. ? read and write buffers to reduce latency and to improve performance. ? 8/16/32 data and 16/20/26 address lines wide static memory support. ? 16 bit and 32 bit wide chip select sdram memory support. ? static memory features include: ? asynchronous page mode read ? programmable wait states ? bus turnaround delay ? output enable and write enable delays ? extended wait ? four chip selects for synchro nous memory and four chip selects for static memory devices. ? power-saving modes dynamically cont rol emc_cke and emc_clk outputs to sdrams. ? dynamic memory self-refresh mode controlled by software. ? controller supports 2048 (a0 to a10), 4096 (a0 to a11), and 8192 (a0 to a12) row address synchronous memory parts. that is typical 512 mb, 256 mb, and 128 mb parts, with 4, 8, 16, or 32 data bits per device. ? separate reset domains allow the for auto-refresh through a chip reset if desired. note: synchronous static memory devices (synchronous burst mode) are not supported. table 5. external memory controller pin configuration parts data bus pins address bus pins control pins sram sdram lpc4088fbd208 LPC4088FET208 lpc4078fbd208 lpc4078fet208 emc_d[31:0] emc_a[25:0] emc_bls[3:0] , emc_cs[3:0] , emc_oe , emc_we emc_ras , emc_cas , emc_dycs[3:0] , emc_clk[1:0], emc_cke[3:0], emc_dqm[3:0] lpc4088fet180 lpc4078fet180 lpc4076fet180 emc_d[15:0] emc_a[19:0] emc_bls[1:0] , emc_cs[1:0] , emc_oe , emc_we emc_ras , emc_cas , emc_dycs[1:0] , emc_clk[1:0], emc_cke[1:0], emc_dqm[1:0] lpc4088fbd144 lpc4078fbd144 lpc4076fbd144 emc_d[7:0] emc_a[15:0] emc_bls[3:2] , emc_cs[1:0] , emc_oe , emc_we not available
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 45 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 7.12 general purpose dma controller the gpdma is an amba ahb compliant periphe ral allowing selected peripherals to have dma support. the gpdma enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. the source and destination areas can each be either a memory region or a peripheral and can be accessed through the ahb master. the gpdma controller allows data transfers between the various on-chip sram areas and supports the sd/mmc card interface, all ssps, the i 2 s, all uarts, the a/d converter, and the d/a converter periphera ls. dma can also be triggered by selected timer match conditions. memory-to-memory transfers and transfers to or from gpio are supported. 7.12.1 features ? eight dma channels. each channel can support an unidirectional transfer. ? 16 dma request lines. ? single dma and burst dma request signals. each peripheral connected to the dma controller can assert either a burst dma request or a single dma request. the dma burst size is set by programming the dma controller. ? memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. ? scatter or gather dma is supported through the use of linked lists. this means that the source and destination areas do not hav e to occupy contiguous areas of memory. ? hardware dma ch annel priority. ? ahb slave dma programming interface. the dma controller is programmed by writing to the dma control regist ers over the ahb slave interface. ? one ahb bus master for transferring data. the interface transfers data when a dma request goes active. ? 32-bit ahb master bus width. ? incrementing or non-incrementing addressing for source and destination. ? programmable dma burst size. the dma burst size can be programmed to more efficiently transfer data. ? internal four-word fifo per channel. ? supports 8, 16, and 32-bit wide transactions. ? big-endian and little-endian support. the dma controller defaults to little-endian mode on reset. ? an interrupt to the processor can be generated on a dma completion or when a dma error has occurred. ? raw interrupt status. the dma error and dma count raw interrupt status can be read prior to masking. 7.13 crc engine the cyclic redundancy check (crc) genera tor with programmable polynomial settings supports several crc standards commonl y used. to save system power and bus bandwidth, the crc engine supports dma transfers.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 46 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 7.13.1 features ? supports three common polynomials crc-ccitt, crc-16, and crc-32. ? crc-ccitt: x 16 + x 12 + x 5 + 1 ? crc-16: x 16 + x 15 + x 2 + 1 ? crc-32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? bit order reverse and 1?s complement programmable setting for input data and crc sum. ? programmable seed number setting. ? supports cpu pio or dma back-to-back transfer. ? accept any size of data width per write: 8, 16 or 32-bit. ? 8-bit write: 1-cycle operation ? 16-bit write: 2-cycle op eration (8-bit x 2-cycle) ? 32-bit write: 4-cycle op eration (8-bit x 4-cycle) 7.14 lcd controller remark: the lcd controller is available on parts lpc4088. the lcd controller provides all of the necessary control signals to interface directly to a variety of color and monochrome lcd panels. both stn (single and dual panel) and tft panels can be operated. the display resolution is selectable and can be up to 1024 ? 768 pixels. several color modes are provided, up to a 24-bit true-color non-palettized mode. an on-chip 512-byte color palette allows reducing bus utilizati on (i.e. memory size of the displayed data) while still supporti ng a large number of colors. the lcd interface includes its own dma controlle r to allow it to operate independently of the cpu and other system functions. a built-in fifo acts as a buffer for display data, providing flexibility for system timing. hardware cursor su pport can furthe r reduce the amount of cpu time needed to operate the display. 7.14.1 features ? ahb master interface to access frame buffer. ? setup and control via a separate ahb slave interface. ? dual 16-deep programmable 64-bit wide fifos for buffering incoming display data. ? supports single and dual-panel monochrome super twisted nematic (stn) displays with 4-bit or 8-bit interfaces. ? supports single and dual-panel color stn displays. ? supports thin film transi stor (tft) color displays. ? programmable display resolution including, but not limited to: 320 ? 200, 320 ? 240, 640 ? 200, 640 ? 240, 640 ? 480, 800 ? 600, and 1024 ? 768. ? hardware cursor support for single-panel displays. ? 15 gray-level monochrome, 3375 color stn, and 32 k color palettized tft support. ? 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome stn. ? 1, 2, 4, or 8 bpp palettized color displays for color stn and tft.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 47 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? 16 bpp true-color non-palettized, for color stn and tft. ? 24 bpp true-color non-palettized, for color tft. ? programmable timing for different display panels. ? 256 entry, 16-bit palette ram, arranged as a 128 ? 32-bit ram. ? frame, line, and pixel clock signals. ? ac bias signal for stn, data enable signal for tft panels. ? supports little and big-endian, and windows ce data formats. ? lcd panel clock may be generated from the peripheral clock, or from a clock input pin. 7.15 ethernet remark: the ethernet block is available on parts lpc4088/78/76. the ethernet block contains a full featur ed 10 mbit/s or 100 mbit/s ethernet mac designed to provide optimized performa nce through the use of dma hardware acceleration. features include a generous suite of control registers, half or full duplex operation, flow control, cont rol frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on lan activity. automatic frame transmission and reception with scatter-gather dma off-loads many operations from the cpu. the ethernet block and the cpu share the arm cortex-m4 d-code and system bus through the ahb-multilayer matrix to access the various on-chip sram blocks for ethernet data, control, and status information. the ethernet block interfaces between an off-chip ethernet phy using the media independent interface (mii) or reduced m ii (rmii) protocol and the on-chip media independent interface management (miim) serial bus. 7.15.1 features ? ethernet standards support: ? supports 10 mbit/s or 100 mbit/s phy dev ices including 10 base-t, 100 base-tx, 100 base-fx, and 100 base-t4. ? fully compliant with ieee standard 802.3. ? fully compliant with 802.3x full duplex flow contro l and half duplex back pressure. ? flexible transmit and receive frame options. ? virtual local area network (vlan) frame support. ? memory management: ? independent transmit and receive buffers memory mapped to shared sram. ? dma managers with scatter/gather dma and arrays of frame descriptors. ? memory traffic optimized by buffering and pre-fetching. ? enhanced ethernet features: ? receive filtering. ? multicast and broadcast frame support for both transmit and receive.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 48 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? optional automatic frame check sequence (fcs) insertion with circular redundancy check (crc) for transmit. ? selectable automatic transmit frame padding. ? over-length frame support for both transmit and receive allows any length frames. ? promiscuous receive mode. ? automatic collision back-off and frame retr ansmission. ? includes power management by clock switching. ? wake-on-lan power management support allows system wake-up: using the receive filters or a magic frame detection filter. ? physical interface: ? attachment of external phy chip through standard mii or rmii interface. ? phy register access is available via the miim interface. 7.16 usb interface remark: the usb device/host/otg controller is available on parts lpc4088/78/76. the usb device-only controller is available on part lpc4074/72. the universal serial bu s (usb) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. the host controller allocates the usb bandwidth to attached devices through a token-based protocol. the bus supports hot plugging and dynamic configuration of the devi ces. all transactions are initiated by the host controller. see section 13.1 for details on typical usb interfacing solutions. 7.16.1 usb device controller the device controller enables 12 mbit/s data exchange with a usb host controller. it consists of a register interface, serial interface engine, endpoint buffer memory, and a dma controller. the serial interface engine dec odes the usb data stream and writes data to the appropriate endpoint buffer. the status of a completed usb transfer or error condition is indicated via status registers. an interrupt is also generated if enabled. when enabled, the dma controller transfers data between the endpoint buffer and the usb ram. 7.16.1.1 features ? fully compliant with usb 2.0 specification (full speed). ? supports 32 physical (16 logical) endpoints with a 4 kb endpoint buffer ram. ? supports control, bulk, interrupt and isochronous endpoints. ? scalable realization of endpoints at run time. ? endpoint maximum packet size selection (up to usb maximum specification) by software at run time. ? supports softconnect and goodlink features. ? while usb is in the suspend mode, the lpc408x/7x can enter one of the reduced power modes and wake up on usb activity. ? supports dma transfers with all on-chip sram blocks on all non-control endpoints.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 49 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? allows dynamic switching betwee n cpu-controlled and dma modes. ? double buffer implementation for bulk and isochronous endpoints. 7.16.2 usb host controller the host controller enables fu ll- and low-speed data exchange with usb devices attached to the bus. it consists of register interface, serial interface engine and dma controller. the register interface complies with the open ho st controller interfac e (ohci) specification. 7.16.2.1 features ? ohci compliant ? two downstream ports ? supports per-port power switching 7.16.3 usb otg controller usb otg is a supplement to the usb 2.0 specification that augments the capability of existing mobile devices and usb peripherals by adding host functiona lity for connection to usb peripherals. the otg controller integrates the host controller, device controller, and a master-only i 2 c interface to implement otg dual-rol e device functionalit y. the dedicated i 2 c interface controls an external otg transceiver. 7.16.3.1 features ? fully compliant with on-the -go supplement to the usb 2.0 specificat ion, revision 1.0a . ? hardware support for host negotiation protocol (hnp). ? includes a programmable timer required for hnp and session request protocol (srp). ? supports any otg transceiver compliant with the otg transceiver specification (cea-2011), rev. 1.0 . 7.17 sd/mmc card interface remark: the sd/mmc card interface is available on parts lpc4088/78/76. the secure digital and multimed ia card interface (mci) allows access to external sd memory cards. the sd card interface conforms to the sd multimedia ca rd specification version 2.11 . 7.17.1 features ? the mci provides all functions specific to the sd/mmc memory card. these include the clock generation unit, power management control, and command and data transfer. ? conforms to multimedia card specification v2.11 . ? conforms to secure digital memory card phys ical layer specification, v0.96.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 50 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? can be used as a multimedia card bus or a secure digital memory card bus host. the sd/mmc can be connected to several multimedia cards or a single secure digital memory card. ? dma supported through the gpdma controller. 7.18 fast general purpose parallel i/o device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically conf igured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back as well as the current state of the port pins. lpc408x/7x use accelera ted gpio functions: ? gpio registers are accessed through the ahb multilayer bus so that the fastest possible i/o timing can be achieved. ? mask registers allow treating sets of por t bits as a group, leaving other bits unchanged. ? all gpio registers are byte and half-word addressable. ? entire port value can be written in one instruction. ? support for cortex-m4 bit banding. ? support for use with the gpdma controller. additionally, any pin on port 0 and port 2 providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. the edge detection is asynchronous, so it may operate when clocks are not present such as during power-down mode. each enabled interrupt can be used to wake up the chip fr om power-down mode. 7.18.1 features ? bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. ? direction control of individual bits. ? all i/o default to inputs after reset. ? pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each gpio pin. 7.19 12-bit adc the lpc408x/7x contain one adc. it is a si ngle 12-bit successi ve approximation adc with eight channels and dma support. 7.19.1 features ? 12-bit successive approximation adc. ? input multiplexing among eight pins. ? power-down mode. ? measurement range v ss to vrefp. ? 12-bit conversion rate: up to 400 khz.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 51 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? individual channels can be selected for conversion. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of input pin or timer match signal. ? individual result registers for each adc channel to reduce interrupt overhead. ? dma support. 7.20 10-bit dac the lpc408x/7x contain one dac. the dac allows to generate a variable analog output. the maximum output value of the dac is vrefp. 7.20.1 features ? 10-bit dac ? resistor string architecture ? buffered output ? power-down mode ? selectable output drive ? dedicated conversion timer ? dma support 7.21 comparator remark: the comparator is available on parts lpc4088/7876. two embedded comparators are available to compare the voltage levels on external pins or against internal voltages. up to four voltages on external pins and several internal reference voltages are selectable on each comparator. additionally, two of the external inputs can be selected to drive an input common on both comparators. 7.21.1 features ? up to five selectable external sources per comparator; fully configurable on either positive or negative comparator input channels. ? 0.9 v internal band gap reference voltage selectable as either positive or negative input on each comparator. ? 32-stage voltage ladder internal reference for selectable voltages on each comparator; configurable on either po sitive or negative comparator input. ? voltage ladder source voltage is selectable from an external pin or the 3.3 v analog voltage supply. ? voltage ladder can be separa tely powered down for applic ations only requiring the comparator function. ? relaxation oscillator ci rcuitry output, for a 55 5 style timer operation. ? individual comparator outputs can be connected to i/o pins. ? separate interrupt for each comparator.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 52 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? edge and level comparator outputs connect to two timers allowing edge counting while a level match has been asserted or measuring the time between two voltage trip points. 7.22 uart0/1/2/3 and usart4 remark: uart0/1/2/3 are available on all part s. usart4 is available on parts lpc4088/78/76. the lpc408x/7x contain five uarts. in addition to standard transmit and receive data lines, uart1 also provides a full modem control handshake interface and support for rs-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. the uarts include a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.22.1 features ? maximum uart data bit rate of 7.5 mbit/s. ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? auto-baud capability. ? fractional divider for baud rate control, auto baud capabilities and fifo control mechanism that enables software flow control implementation. ? support for rs-485/9-bit/eia-485 mode and multiprocessor addressing. ? all uarts have dma support for both transmit and receive. ? uart1 equipped with standard modem interface signals. this module also provides full support for hardware flow control (auto-cts/rts). ? usart4 includes an irda mode to support infrared communication. ? usart4 supports synchronous mode and a smart card mode conforming to iso7816-3. 7.23 spifi the spi flash interface allows low-cost serial flash memories to be connected to the arm cortex-m4 processor with little performance penalty compared to parallel flash devices with higher pin count. the entire flash content is ac cessible as normal memory using byte, halfword, and word accesses by the processor and/or dma channels. spifi provides sufficient flexibility to be compatible with co mmon flash devices and includes extensions to help insure compatibility with future devices.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 53 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 7.23.1 features ? quad spi flash interface (spifi ) interface to external flash. ? transfer rates of up to spifi_clk/2 bytes per second. ? code in the serial flash memory can be ex ecuted as if it was in the cpu?s internal memory space. this is accomplished by ma pping the external flash memory directly into the cpu memory space. ? supports 1-, 2-, and 4-bit bidirectional serial protocols. ? half-duplex protocol compatible with various vendors and devices. ? supported by a driver library available from nxp semiconductors. 7.24 ssp serial i/o controller the lpc408x/7x contain three ssp contro llers. the ssp controller is capable of operation on a spi, 4-wire ssi, or microwire bus . it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. the ssp supports full duplex transfers, wi th frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.24.1 features ? maximum ssp speed of 60 mbit/s (m aster) or 10 mbit/s (slave) ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame ? dma transfers supported by gpdma 7.25 i 2 c-bus serial i/o controllers the lpc408x/7x contain three i 2 c-bus controllers. the i 2 c-bus is bidirectional for inter-ic control using only two wires: a serial clock line (scl) and a serial data line (sda). each de vice is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 7.25.1 features ? all i 2 c-bus controllers can use standard gpio pins with bit rates of up to 400 kbit/s (fast i 2 c-bus). the i 2 c0-bus interface uses special open-drain pins with bit rates of up to 400 kbit/s.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 54 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? the i 2 c-bus interface supports fast-mode plus wit h bit rates up to 1 mbit/s for i2c0 using pins p5[2] and p5[3]. ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? both i 2 c-bus controllers support multiple address recognition and a bus monitor mode. 7.26 i 2 s-bus serial i/o controllers the lpc408x/7x contain one i 2 s-bus interface. the i 2 s-bus provides a standard communication interface for digital audio applications. the i 2 s-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. the basic i 2 s connection has one master, which is always the master, and one slave. the i 2 s interface on the lpc408x/7x provides a separate transmit and receive channel, each of which can o perate as either a master or a slave. 7.26.1 features ? the interface has separate input/output chan nels each of which can operate in master or slave mode. ? capable of handling 8-bit, 16-bit, and 32-bit word sizes. ? mono and stereo audio data supported. ? the sampling frequency can range from 16 khz to 48 khz (16, 22.05, 32, 44.1, 48) khz. ? configurable word select period in master mode (separately for i 2 s input and output). ? two 8 word fifo data buffers are provided, one for transmit and one for receive. ? generates interrupt requests when buffer levels cross a programmable boundary. ? two dma requests, controlled by programma ble buffer levels. these are connected to the gpdma block. ? controls include reset, stop and mute options separately for i 2 s input and i 2 s output. 7.27 can controller and acceptance filters the lpc408x/7x contain one can controller with two channels.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 55 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller the controller area network (can) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. its domain of application ranges from high-speed ne tworks to low cost multiplex wiring. the can block is intended to support multip le can buses simultaneously, allowing the device to be used as a gateway, switch, or router between two of can buses in industrial or automotive applications. each can controller has a regi ster structure sim ilar to the nxp sja1 000 and the pelican library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the arm environment. the main operational difference is that the recognition of received identifiers, known in can terminology as acceptance filtering, has been removed from the can controllers and centralized in a global acceptance filter. 7.27.1 features ? two can controllers and buses. ? data rates to 1 mbit/s on each bus. ? 32-bit register and ram access. ? compatible with can specification 2.0b, iso 11898-1 . ? global acceptance filter recognizes 11-bit and 29-bit receive identifiers for all can buses. ? acceptance filter can provide fullcan-s tyle automatic reception for selected standard identifiers. ? fullcan messages can gen erate interrupts. 7.28 general purpose 32-bit time rs/external event counters the lpc408x/7x include four 32-bit timer/counters. the timer/counter is design ed to count cycles of th e system derived clock or an externally-supplied clock. it can optionally generate interrupts , generate timed dma requests, or perform other actions at spec ified timer values, based on four match registers. each timer/counter al so includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.28.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation. ? two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities:
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 56 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? up to two match registers can be used to generate timed dma requests. 7.29 pulse width modulator (pwm) the lpc408x/7x contain two standard pwms. the pwm is based on the standard timer block and inherits all of its features, although only the pwm function is pinned out on the lpc408x/7x. the timer is designed to count cycles of the system derived clock and optiona lly switch pins, gene rate interrupts or perform other actions when specified timer va lues occur, based on seven match registers. the pwm function is in addition to these feat ures, and is based on match register events. the ability to separately contro l rising and falling edge locations allo ws the pwm to be used for more applications. for instance, mu lti-phase motor control typically requires three non-overlapping pwm outputs with individual control of all three pulse widths and positions. two match registers can be used to provide a single edge controlled pwm output. one match register (pwmmr0) controls the pwm cycle rate, by resetting the count upon match. the other match register controls th e pwm edge position. additional single edge controlled pwm outputs require only one match re gister each, since the repetition rate is the same for all pwm outputs. multiple single edge contro lled pwm outputs will all have a rising edge at the beginning of each pwm cycle, when an pwmmr0 match occurs. three match registers can be used to provid e a pwm output with both edges controlled. again, the pwmmr0 match register contro ls the pwm cycle rate. the other match registers control the two pwm edge positi ons. additional double edge controlled pwm outputs require only two match registers each, si nce the repetition rate is the same for all pwm outputs. with double edge controlled pwm outputs, spec ific match registers control the rising and falling edge of the output. this allows both positive going pwm pulses (when the rising edge occurs prior to the falling edge), and negative goi ng pwm pulses (when the falling edge occurs prior to the rising edge). 7.29.1 features ? lpc408x/7x has two pwm blocks with counte r or timer operat ion (may use the peripheral clock or one of the capture inputs as the clock source). ? seven match registers allow up to 6 single edge controlled or 3 double edge controlled pwm outputs, or a mix of bot h types. the match registers also allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 57 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? supports single edge controlled and/or double edge controlled pwm outputs. single edge controlled pwm outputs all go high at the beginning of each cycle unless the output is a constant low. double edge controlled pwm outputs can have either edge occur at any position within a cycle. this a llows for both positive going and negative going pulses. ? pulse period and width can be any number of timer counts. this allows complete flexibility in the trad e-off between resolution and re petition rate. all pwm outputs will occur at the same repetition rate. ? double edge controlled pwm outputs can be programmed to be either positive going or negative going pulses. ? match register updates are synchronized wit h pulse outputs to prevent generation of erroneous pulses. software must ?release? new match values before they can become effective. ? may be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler if the pwm mode is not enabled. 7.30 motor control pwm the lpc408x/7x contain one motor control pwm. the motor control pwm is a specialized pwm supporting 3-phase motors and other combinations. feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. an abort input is also provided that causes the pwm to immediately release all motor drive ou tputs. at the same time, the motor control pwm is highly configurable for other genera lized timing, counting, capture, and compare applications. the maximum pwm speed is determined by the pwm resolution (n) and the operating frequency f: pwm speed = f/2 n (see ta b l e 6 ). 7.31 quadrature encoder interface (qei) remark: the qei is available on parts lpc4088/78/76. a quadrature encoder, also known as a 2-chan nel incremental encoder, converts angular displacement into two pulse signals. by mo nitoring both the number of pulses and the relative phase of the two signals, the user ca n track the position, direction of rotation, and velocity. in addition, a third channel, or index signal, can be used to reset the position counter. the quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over ti me and determine direction of rotation. in addition, the qei can capture the velocity of the encoder wheel. 7.31.1 features ? tracks encoder position. table 6. pwm speed at operating frequency 120 mhz pwm resolution pwm speed 6 bit 1.875 mhz 8 bit 0.468 mhz 10 bit 0.117 mhz
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 58 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? increments/decrements depending on direction. ? programmable for 2 ? or 4 ? position counting. ? velocity capture using built-in timer. ? velocity compare function with ?less than? interrupt. ? uses 32-bit registers for position and velocity. ? three position compare registers with interrupts. ? index counter for re volution counting. ? index compare register with interrupts. ? can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. ? digital filter with prog rammable delays for encoder input signals. ? can accept decoded signal inputs (clk and direction). ? connected to apb. 7.32 arm cortex-m4 system tick timer the arm cortex-m4 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a 10 ms interval. in the lp c408x/7x, this timer can be clocked from the internal ahb clock or from a device pin. 7.33 windowed watc hdog timer (wwdt) the purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.33.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect feed sequence causes reset or interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source is a dedicated watc hdog oscillator, which is always running if the watchdog timer is enabled.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 59 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 7.34 rtc and backup registers the rtc is a set of counters for measuring ti me when system power is on, and optionally when it is off. the rtc on the lpc408x/7x is designed to have extremely low power consumption, i.e. less than 1 ? a. the rtc will typically run from the main chip power supply conserving battery po wer while the rest of the de vice is powered up. when operating from a batter y, the rtc will continue working do wn to 2.1 v. battery power can be provided from a standard 3 v lithium button cell. an ultra-low power 32 khz oscillator will provid e a 1 hz clock to the time counting portion of the rtc, moving most of the power cons umption out of the time counting function. the rtc includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less th an 1 second per day error when o perated at a constant voltage and temperature. the rtc contains a small set of backup regi sters (20 bytes) for holding data while the main part of the lpc408x/7x is powered off. the rtc includes an alarm function that can wake up the lpc408x/7x from all reduced power modes with a time resolution of 1 s. 7.34.1 features ? measures the passage of time to maintain a calendar and clock. ? ultra low power design to support battery powered systems. ? provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? dedicated power supply pin can be connected to a battery or to the main 3.3 v. ? periodic interrupts can be generated from increments of any field of the time registers. ? backup registers (20 bytes) powered by vbat. ? rtc power supply is isolated from the rest of the chip. 7.35 event monitor/recorder the event monitor/recorder allows recording of tampering events in sealed product enclosures. sensors report any attempt to open the enclosure, or to tamper with the device in any other way. the event monitor/recorder stores records of such events when the device is powered only by the backup battery. 7.35.1 features ? supports three digital event inputs in the vbat power domain. ? an event is defined as a level change at the digital event inputs. ? for each event channel, two timestamps mark the first and the last occurrence of an event. each channel also has a dedicated counter tracking the total number of events. timestamp values are taken from the rtc. ? runs in vbat power domain, independent of system power supply. the event/recorder/monitor can therefore operate in deep power-down mode. ? very low power consumption.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 60 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? interrupt available if system is running. ? a qualified event can be used as a wake-up trigger. ? state of event interrupts accessible by software through gpio. 7.36 clocking and power control 7.36.1 crystal oscillators the lpc408x/7x include four independent oscillators. these are the main o scillator, the irc oscillator, the watchdog osc illator, and the rtc oscillator. following reset, the lpc408x/7x will operate from the internal rc o scillator until switched by software. this allows systems to operate without any external crystal and the boot loader code to operate at a known frequency. see figure 8 for an overview of the lpc408x/7x clock generation. fig 8. lpc408x/7x clock generation block diagram main pll0 irc oscillator main oscillator (osc_clk) clksrcsel (system clock select) sysclk pll_clk cclksel (cpu clock select) 002aag737 pll_clk alt pll1 cpu clock divider alt_pll_clk cclk peripheral clock divider pclk emc clock divider emc_clk sysclk alt_pll_clk pll_clk usbclksel (usb clock select) usb clock divider usb_clk sysclk lpc408x/7x
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 61 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 7.36.1.1 internal rc oscillator the irc may be used as the clock that drives the pll and subsequently the cpu. the nominal irc frequency is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. upon power-up or any chip reset, the lpc408x/7x use the irc as the clock source. software may later switch to one of the other available clock sources. 7.36.1.2 main oscillator the main oscillator can be used as the clock so urce for the cpu, with or without using the pll. the main oscillator al so provides the clock sour ce for the alternate pll1. the main oscillator operates at fr equencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the main pll. the clock selected as the pll inpu t is pllclkin. the arm processor clock frequency is referred to as cclk elsewhere in this document. the frequencies of pllclkin and cclk are the same value unless the pll is active and connected. the clock frequency for each peripheral can be selected individually and is referred to as pclk. refer to section 7.36.2 for additional information. 7.36.1.3 rtc oscillator the rtc oscillator provides a 1 hz clock to the rtc and a 32 khz cl ock output that can be output on the clkout pin in order to allow trimming the rtc oscillator without interference from a probe. 7.36.1.4 watchdog oscillator the watchdog timer has a dedicated oscillator that prov ides a 500 khz clock to the watchdog timer that is always running if the watchdog timer is enabled. the watchdog oscillator clock can be output on the clkout pin in order to allow observe its frequency. in order to allow watchdog timer operation with minimum power consumption, which can be important in redu ced power modes, the watchdog o scillator frequency is not tightly controlled. the watchdog osc illator frequency will vary over temperature and power supply within a particular part, and may vary by processing across different parts. this variation should be taken into account when determining watchdog reload values. within a particular part, temperature and power supply variations can produce up to a ? 17 % frequency variation. frequency variation between devices under the same operating conditions can be up to ? 30 %. 7.36.2 main pll (pll0) and alternate pll (pll1) pll0 (also called the main pll) and pll1 (als o called the alternate pll) are functionally identical but have somewhat different input possibilities and output connections. these possibilities are shown in figure 8 . the main pll can receive its input from either the irc or the main oscillator and c an potentially be used to pr ovide the clocks to nearly everything on the device. the al ternate pll receives its input only from the main oscillator and is intended to be used as an alternate source of clocking to the usb. the usb has timing needs that may not alwa ys be filled by the main pll.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 62 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller both plls are disabled and powered off on reset. if the alternate pll is left disabled, the usb clock can be supplied by pll0 if everything is set up to provide 48 mhz to the usb clock through that route. the source for ea ch clock must be selected via the clksel registers and can be further reduce d by clock dividers as needed. pll0 accepts an input clock frequency from either the irc or the main oscillator. if only the main pll is used, then its output frequency must be an integer multiple of all other clocks needed in the system. pl l1 takes its input only from th e main oscillator, requiring an external crystal in the range of 10 to 25 mhz. in each pll, the current controlled oscillator (cco) operates in t he range of 156 mhz to 320 mh z, so there are additional dividers to bring the output down to the desired frequencies. the minimum output divider value is 2, insuring th at the output of the plls have a 50 % duty cycle. if the usb is used, the possibilities for the cp u clock and other clocks will be limited by the requirements that the frequency be precise and very low jitter, and that the pll0 output must be a multiple of 48 mhz. ev en multiples of 48 mhz that are within the operating range of the pll ar e 192 mhz and 288 mhz. also, only the main oscillator in conjunction with the pll can meet the precision and jitter specifications for usb. it is due to these limitations that th e alternate pll is provided. the alternate pll accepts an input clock freque ncy from the main oscillator in the range of 10 mhz to 25 mhz only. when used as the u sb clock, the input frequency is multiplied up to a multiple of 48 mhz (192 mhz or 288 mhz as described above). 7.36.3 wake-up timer the lpc408x/7x begin operation at power-up and when awakened from power-down mode by using the 12 mhz irc os cillator as the cloc k source. this allo ws chip operation to resume quickly. if the main oscillator or the pll is neede d by the applicat ion, software will need to enable these features and wait for them to st abilize before they are used as a clock source. when the main oscillator is init ially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. this is im portant at power on, all types of reset, and whenever any of the aforemen tioned functions are turned off for any reason. since the oscillator and other functions are turned off during power-down mode, any wake-up of the processor from power-down mode makes use of the wake-up timer. the wake-up timer mo nitors the crystal oscillator to check whether it is safe to begin code execution. when power is applied to the chip, or when some event caused the chip to exit power-down mode, some time is required for the oscilla tor to produce a signal of sufficient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd(3v3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the ch aracteristics of the oscillator it self under the existing ambient conditions. 7.36.4 power control the lpc408x/7x support a variety of power control features. there are four special modes of processor power reduction: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. the cpu clock ra te may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power ve rsus processing speed based on application
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 63 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller requirements. in addition, the peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. each of the peripherals has its own clock divider wh ich provides even better power control. the integrated pmu (power management unit) automatically adjusts internal regulators to minimize power consumption during sleep, deep-sleep, power-down, and deep power-down modes. the lpc408x/7x also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the rtc and a small set of registers for storing data during any of the power-down modes. 7.36.4.1 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence othe r than re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. the dma controller can continue to work in sleep mode and has access to the peripheral rams and all peripheral registers. the flash memory and the main sram are not available in sleep mode, they are disabled in order to save power. wake-up from sleep mode will occur when ever any enabled interrupt occurs. 7.36.4.2 deep-sleep mode in deep-sleep mode, the oscilla tor is shut down and the chip receives no internal clocks. the processor state and registers, peripheral registers, and internal sram values are preserved throughout deep-sleep mode and the logic levels of chip pins remain static. the output of the irc is disabl ed but the irc is not powered down to allow fast wake-up. the rtc oscillator is not stopped because the rtc interrupts may be used as the wake-up source. the pll is automatically turned off and disconnected. the clock divider registers are automati cally reset to zero. the deep-sleep mode can be terminated a nd normal operation resumed by either a reset or certain specific inte rrupts that are able to function without clocks. since all dynamic operation of the chip is suspended, deep-sleep mode reduces chip power consumption to a very low value. power to th e flash memory is left on in deep-sleep mode, allowing a very quick wake-up. wake-up from deep-sleep mode can initiated by the nmi, external interrupts eint0 through eint3 , gpio interrupts, the ethernet wake-on-lan interrupt, brownout detect, an rtc alarm interrupt, a usb input pin trans ition (usb activity interrupt), a can input pin transition, or a watchdog timer time-out, when the related interrupt is enabled. wake-up will occur whenever an y enabled interrupt occurs.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 64 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller on wake-up from deep-sleep mode, the code execution an d peripherals activities will resume after four cycles expire if the irc was used before entering deep-sleep mode. if the main external oscillato r was used, the code execution will resume when 4096 cycles expire. pll and clock dividers need to be reconfigured accordingly. 7.36.4.3 power-down mode power-down mode does everythi ng that deep-sleep mode does but also turns off the power to the irc oscillator an d the flash memory. this save s more power but requires waiting for resumption of flash operation befo re execution of code or data access in the flash memory can be accomplished. when the chip enters power-down mode, the irc, the main oscillator, and all clocks are stopped. the rtc remains running if it has been enabled and rtc interrupts may be used to wake up the cpu. the flash is forced into power-down mode. the plls are automatically turned off and the clock select ion multiplexers are se t to use the system clock sysclk (the reset state). the clock divider control registers are aut omatically reset to zero. if the watchdog timer is running, it will continue running in power-down mode. on the wake-up of power-down mode, if the irc was used before entering power-down mode, it will take irc 60 ? s to start-up. after th is four irc cycles will expire before the code execution can then be resumed if the code was running from sram. in the meantime, the flash wake-up timer then co unts 12 mhz irc clock cycles to make the 100 ? s flash start-up time. when it times out, access to the flash will be allowed. users need to reconfigure the pll and clock dividers accordingly. 7.36.4.4 deep power-down mode the deep power-down mode can only be entered from the rtc block. in deep power-down mode, power is shut off to the entire chip with the exception of the rtc module and the reset pin. to optimize power conservation, the user ha s the additional option of turning off or retaining power to th e 32 khz oscillator. it is also possibl e to use external circuitry to turn off power to the on-chip regulator via the v dd(reg)(3v3) pins and/or the i/o power via the v dd(3v3) pins after entering deep power-down mode. power must be restored before device operation can be restarted. the lpc408x/7x can wake up from deep power-down mode via the reset pin or an alarm match event of the rtc. 7.36.4.5 wake-up interrupt controller (wic) the wic allows the cpu to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in deep-sleep, power-down, and deep power-down modes. the wic works in connection with the nested vectored interrupt controller (nvic). when the cpu enters deep-sleep, power-down, or deep power-down mode, the nvic sends a mask of the current interrupt situation to t he wic.this mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. with this information, the wic simply notices when one of the interrupts has occurred and then it wakes up the cpu. the wic eliminates the need to periodically wake up the cpu and poll the interrupts resulting in additional power savings.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 65 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 7.36.5 peripheral power control a power control for peripherals feature allows i ndividual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. 7.36.6 power domains the lpc408x/7x provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the rtc and the backup registers. on the lpc408x/7x, i/o pads are powered by v dd(3v3) , while v dd(reg)(3v3) powers the on-chip voltage regulator which in turn provides power to the cpu and most of the peripherals. depending on the lpc408x/7x application, a design can use two power options to manage power consumption. the first option assumes that power consumptio n is not a concern and the design ties the v dd(3v3) and v dd(reg)(3v3) pins together. this approach requires only one 3.3 v power supply for both pads, the cpu, and peripherals. while this solution is simple, it does not support powering down the i/o pad ring ?on the fly? while keeping the cpu and peripherals alive. the second option uses two power supplie s; a 3.3 v supply for the i/o pads (v dd(3v3) ) and a dedicated 3.3 v supply for the cpu (v dd(reg)(3v3) ). having the on-chip voltage regulator powered independently from the i/o pad ring enables shutting down of the i/o pad power supply ?on the fly? while the cp u and peripherals stay active. the vbat pin supplies power only to the rtc domain. the rtc requires a minimum of power to operate, which can be supplied by an external battery. the device core power (v dd(reg)(3v3) ) is used to operate the rtc whenever v dd(reg)(3v3) is present. there is no power drain from the rtc battery when v dd(reg)(3v3) is available and v dd(reg)(3v3) > v bat .
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 66 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 7.37 system control 7.37.1 reset reset has four sources on the lpc408x/7x: the reset pin, the watchdog reset, power-on reset (por), and the browno ut detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the wake-up timer (see description in section 7.36.3 ), causing reset to remain asserted un til the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed it s initialization. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. fig 9. power distribution real-time clock backup registers regulator 32 khz oscillator power selector ultra-low power regulator rtc power domain main power domain 002aag738 rtcx1 vbat (typical 3.0 v) v dd(reg)(3v3) (typical 3.3 v) rtcx2 v dd(3v3) v ss to memories, peripherals, oscillators, plls to core to i/o pads adc dac adc power domain v dda vrefp v ssa lpc408x/7x
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 67 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 7.37.2 brownout detection the lpc408x/7x include 2-stage monitoring of the voltage on the v dd(reg)(3v3) pins. if this voltage falls below 2.95 v, the bod asserts an interrupt signal to the vectored interrupt controller. this signal can be enabled for inte rrupt in the interrupt enable register in the nvic in order to cause a cpu in terrupt; if not, software can monitor the signal by reading a dedicated status register. the second stage of low-voltage detection a sserts reset to inactivate the lpc408x/7x when the voltage on the v dd(reg)(3v3) pins falls below 2.65 v. this reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. the bo d circuit maintains this reset down below 1 v, at which point the power-on reset circuitry maintains the overall reset. both the 2.95 v and 2.65 v thresholds include some hysteresis. in normal operation, this hysteresis allows the 2.95 v de tection to reliably interrupt, or a regularly executed event loop to sense the condition. 7.37.3 code security (code read protection - crp) this feature of the lpc408x/7x allows user to enable different levels of security in the system so that access to the on-chip flash and use of the jtag and isp can be restricted. when needed, crp is invoked by programming a specific pattern into a dedicated flash location. iap commands are not affected by the crp. there are three levels of the code read protection. crp1 disables access to chip via the jtag and allows partial flash update (excluding flash sector 0) using a limited set of the is p commands. this mode is useful when crp is required and flash field updates are needed but all sectors can not be erased. crp2 disables access to chip via the jtag and only allows full flash erase and update using a reduced set of the isp commands. running an application with level crp3 selected fully disa bles any access to chip via the jtag pins and the isp. this mode effectively disables isp override using p2[10] pin, too. it is up to the user?s application to provide (if needed) flash update mechanism using iap calls or call reinvoke isp command to enable flash update via uart0. 7.37.4 apb interface the apb peripherals are split into two separa te apb buses in order to distribute the bus bandwidth and thereby reducing stalls caus ed by contention between the cpu and the gpdma controller. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 68 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 7.37.5 ahb multilayer matrix the lpc408x/7x use an ahb multilayer matrix . this matrix connec ts the instruction (i-code) and data (d-code) cpu buses of th e arm cortex-m4 to the flash memory, the main (32 kb) static ram, and the boot rom. the gpdma can also access all of these memories. additionally, the matrix connec ts the cpu system bus and all of the dma controllers to the various peripheral functions. 7.37.6 external interrupt inputs the lpc408x/7x include up to 30 edge sensitive interrupt inputs combined with one level sensitive external interrupt input as selectable pin function. the external interrupt input can optionally be used to wake up the processor from power-down mode. 7.37.7 memory mapping control the cortex-m4 incorporates a me chanism that allows remapping the interrupt vector table to alternate locations in the memory map. th is is controlled via the vector table offset register contained in the nvic. the vector table may be located anywhere within the bottom 1 gb of cortex-m4 address space. the vector table must be located on a 128 word (512 byte) boundary because the nvic on the lpc408x/7x is configured for 128 total interrupts. 7.38 debug control debug and trace functions are integrated in to the arm cortex-m4. serial wire debug and trace functions are supported in addition to a standard jtag debug and parallel trace functions. the arm cortex-m4 is configured to support up to eight breakpoints and four watch points. 8. limiting values table 7. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) external rail 2.4 3.6 v v dd(reg)(3v3) regulator supply voltage (3.3 v) 2.4 3.6 v v dda analog 3.3 v pad supply voltage ? 0.5 +4.6 v v i(vbat) input voltage on pin vbat for the rtc ? 0.5 +4.6 v v i(vrefp) input voltage on pin vrefp ? 0.5 +4.6 v v ia analog input voltage on adc related pins ? 0.5 +5.1 v v i input voltage 5 v tolerant digital i/o pins; v dd(3v3) ? 2.4v [2] ? 0.5 +5.5 v v dd(3v3) ? 0 v ? 0.5 +3.6 v other i/o pins [2] [3] ? 0.5 v dd(3v3) + 0.5 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 69 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] not to exceed 4.6 v. [4] the maximum non-operating storage temperature is different t han the temperature for required shelf life which should be dete rmined based on the required shelf lifetime. please refe r to the jedec spec for further details. [5] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. i latch i/o latch-up current ? (0.5v dd(3v3) ) < v i < (1.5v dd(3v3) ); t j < 125 ? c - 100 ma t stg storage temperature non-operating [4] ? 65 +150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [5] ? 4000 v table 7. limiting values ?continued in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 70 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 9. thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation t j t amb p d r th j a ? ?? ? ?? += table 8. thermal characteristics v dd = 3.0 v to 3.6 v; t amb = ? ? ? symbol parameter conditions min typ max unit t j(max) maximum junction temperature --125 ? c table 9. thermal resistance (lqfp packages) t amb = ? ? ? thermal resistance value ( ? c/w): 15 % lqfp80 lqfp144 lqfp208 ? ja jedec (4.5 in ? 4 in) 0 m/s 41 31 27 1 m/s 35 28 25 2.5 m/s 32 26 24 single-layer (4.5 in ? 3 in) 0 m/s 61 43 35 1 m/s 47 35 31 2.5 m/s 43 33 29 ? jc 7.8 9.2 10.5 ? jb 11.6 13.5 15.2
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 71 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller table 10. thermal resistance value (tfbga packages) t amb = ? 40 ? c to +85 ? c unless otherwise specified. thermal resistance value ( ? c/w): 15 % tfbga180 tfbga208 ? ja jedec (4.5 in ? 4 in) 0 m/s 47 43 1 m/s 39 37 2.5 m/s 35 33 8-layer (4.5 in ? 3 in) 0 m/s 39 37 1 m/s 35 33 2.5 m/s 31 30 ? jc 8.5 7.4 ? jb 13 16
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 72 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 10. static characteristics table 11. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit supply pins v dd(3v3) supply voltage (3.3 v) external rail [2] 2.4 3.3 3.6 v v dd(reg)(3v3) regulator supply voltage (3.3 v) 2.4 3.3 3.6 v v dda analog 3.3 v pad supply voltage 2.7 3.3 3.6 v v i(vbat) input voltage on pin vbat [3] 2.1 3.0 3.6 v v i(vrefp) input voltage on pin vrefp 2.7 3.3 v dda v i dd(reg)(3v3) regulator supply current (3.3 v) active mode; code while(1){} executed from flash; all peripherals disabled pclk = cclk/4 cclk = 12 mhz; pll disabled [4] [5] -7-m a cclk = 120 mhz; pll enabled [4] [6] -5 1-m a active mode; code while(1){} executed from flash; all peripherals enabled; pclk = cclk/4 cclk = 12 mhz; pll disabled [4] [5] 14 cclk = 120 mhz; pll enabled [4] [6] 100 ma sleep mode [4] [7] -5-m a deep-sleep mode [4] [8] -5 5 0- ? a power-down mode [4] [8] -2 8 0- ? a i bat battery supply current rtc running; part powered down; v dd(reg)(3v3) =0 v; v i(vbat) = 3.0 v; v dd(3v3) = 0 v. [9] - 1- ? a part powered; v dd(reg)(3v3) = 3.3 v; v i(vbat) = 3.0 v [10] <10 na
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 73 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller standard port pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled - 0.5 10 na i ih high-level input current v i =v dd(3v3) ; on-chip pull-down resistor disabled - 0.5 10 na v i input voltage pin configured to provide a digital function [14] [15] [16] 0- 5 . 0v v o output voltage output active 0 - v dd(3v3) v v ih high-level input voltage 0.7v dd(3v3) --v v il low-level input voltage - - 0.3v dd(3v3) v v hys hysteresis voltage 0.4 - - v v oh high-level output voltage i oh = ? 4 ma v dd(3v3) ? 0.45 --v v ol low-level output voltage i ol = 4 m a --0 . 4 5v i oh high-level output current v oh =v dd(3v3) ? 0.4 v ? 4--ma i ol low-level output current v ol = 0 . 4 v 4--m a i ohs high-level short-circuit output current v oh =0v [17] --? 50 ma i ols low-level short-circuit output current v ol =v dd(3v3) [17] --6 0m a i pd pull-down current v i =5v 10 50 150 ? a i pu pull-up current v i =0v ? 15 ? 50 ? 85 ? a v dd(3v3) lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 74 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] for usb operation 3.0 v ? v dd((3v3) ? 3.6 v. guaranteed by design. [3] the rtc typically fails when v i(vbat) drops below 1.6 v. [4] v dd(reg)(3v3) = 3.3 v; t amb =25 ? c for all power consumption measurements. [5] boost control bits in the pboost register set to 0x0 (see lpc408x/7x user manual ). [6] boost control bits in the pboost register set to 0x3 (see lpc408x/7x user manual ). [7] irc running at 12 mhz; main osci llator and pll disabled; pclk = cclk/4. [8] bod disabled. [9] on pin vbat; v dd(reg)(3v3) = v dd(3v3) = v dda = 0; t amb =25 ? c. [10] on pin vbat; v dd(reg)(3v3) = v dd(3v3) = v dda = 3.3 v; t amb =25 ? c. [11] all internal pull-ups disabled. all pi ns configured as output and driven low. v dd(3v3) = 3.3 v; t amb =25 ? c. [12] v dda = 3.3 v; t amb =25 ? c. [13] v i(vrefp) = 3.3 v; t amb =25 ? c. [14] including voltage on outputs in 3-state mode. [15] v dd(3v3) supply voltages must be present. [16] 3-state outputs go into 3-state mode in deep power-down mode. [17] allowed as long as the current limit does not exceed the maximum current allowed by the device. [18] to v ss . [19] 3.0 v ? v dd(3v3) ? 3.6 v. v cm differential common mode voltage range includes v di range [19] 0.8 - 2.5 v v th(rs)se single-ended receiver switching threshold voltage [19] 0.8 - 2.0 v v ol low-level output voltage for low-/full-speed r l of 1.5 k ? to 3.6 v [19] --0 . 1 8v v oh high-level output voltage (driven) for low-/full-speed r l of 15 k ? to gnd [19] 2.8 - 3.5 v c trans transceiver capacitance pin to gnd [19] --2 0p f oscillator pins (see section 13.2 ) v i(xtal1) input voltage on pin xtal1 ? 0.5 1.8 1.95 v v o(xtal2) output voltage on pin xtal2 ? 0.5 1.8 1.95 v v i(rtcx1) input voltage on pin rtcx1 ? 0.5 - 3.6 v v o(rtcx2) output voltage on pin rtcx2 ? 0.5 - 3.6 v table 11. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 75 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 10.1 power consumption conditions: bod disabled. fig 10. deep-sleep mode: typical regulator supply current i dd(reg)(3v3) versus temperature conditions: bod disabled. fig 11. power-down mode: typical regulator supply current i dd(reg)(3v3) versus temperature temperature (c) -40 85 35 10 60 -15 002aah051 0.7 1.1 1.5 0.3 v dd(reg)(3v3) = 3.6 v 3.3 v 3.0 v 2.4 v i dd(reg)(3v3) (ma) temperature (c) -40 85 35 10 60 -15 002aah052 300 600 900 0 v dd(reg)(3v3) = 3.6 v 3.3 v 3.0 v 2.4 v i dd(reg)(3v3) (a)
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 76 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller conditions: v dd(reg)(3v3) = v dda = v dd(3v3) = 0; v bat = 3.0 v. fig 12. part powered off: typica l battery supply current (i bat ) versus temperature 002aah074 temperature (c) -40 85 35 10 60 -15 0.8 1.6 0.4 1.2 2.0 0 i bat (a)
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 77 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 10.2 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the pconp register. all other blocks are disabled and no code is ex ecuted. measured on a typical sample at t amb =25 ? c. the peripheral clock was set to pclk = cclk/4 with cclk = 12 mhz, 48 mhz, and 120 mhz. the combined current of several peripherals running at the same time can be less than the sum of each individual peripheral current measured separately. table 12. power consumption for individual analog and digital blocks t amb =25 ? c; v dd(reg)(3v3) = v dd(3v3) = v dda = 3.3 v; pclk = cclk/4. peripheral conditions typical supply current in ma 12 mhz [1] 48 mhz [1] 120 mhz [2] timer0 0.01 0.06 0.15 timer1 0.02 0.07 0.16 timer2 0.02 0.07 0.17 timer3 0.01 0.07 0.16 timer0 + timer1 + timer2 + timer3 0.07 0.28 0.67 uart0 0.05 0.19 0.45 uart1 0.06 0.24 0.56 uart2 0.05 0.2 0.47 uart3 0.06 0.23 0.56 usart4 0.07 0.27 0.66 uart0 + uart1 + uart2 + uart3 + usart4 0.29 1.13 2.74 pwm0 + pwm1 0.08 0.31 0.75 motor control pwm 0.04 0.15 0.36 i2c0 0.01 0.03 0.08 i2c1 0.01 0.03 0.1 i2c2 0.01 0.03 0.08 i2c0 + i2c1 + i2c2 0.02 0.1 0.26 ssp0 0.03 0.1 0.26 ssp1 0.02 0.11 0.27 dac 0.3 0.31 0.33 adc (12 mhz clock) 1.51 1.61 1.7 comparator 0.01 0.03 0.06 can1 0.11 0.44 1.08 can2 0.1 0.4 0.98 can1 + can2 0.15 0.59 1.44 dma pclk = cclk 1.1 4.27 10.27 qei 0.02 0.11 0.28 gpio 0.4 1.72 4.16 lcd 0.99 3.84 9.25
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 78 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [1] boost control bits in the pboost register set to 0x0 (see lpc178x/7x user manual um10470 ). [2] boost control bits in the pboost register set to 0x3 (see lpc178x/7x user manual um10470 ). i2s 0.04 0.18 0.46 emc 0.82 3.17 7.63 rtc 0.01 0.01 0.05 usb + pll1 0.62 0.97 1.67 ethernet pcenet bit set to 1 in the pconp register 0.54 2.08 5.03 table 12. power consumption for individual analog and digital blocks ?continued t amb =25 ? c; v dd(reg)(3v3) = v dd(3v3) = v dda = 3.3 v; pclk = cclk/4. peripheral conditions typical supply current in ma 12 mhz [1] 48 mhz [1] 120 mhz [2]
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 79 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 10.3 electrical pi n characteristics conditions: v dd(reg)(3v3) = v dd(3v3) = 3.3 v; standard port pins. fig 13. typical high-level output voltage v oh versus high-level output source current i oh conditions: v dd(reg)(3v3) = v dd(3v3) = 3.3 v; standard port pins. fig 14. typical low-l evel output current i ol versus low-level output voltage v ol i oh (ma) 0 24 16 8 002aaf112 2.8 2.4 3.2 3.6 v oh (v) 2.0 t = 85 c 25 c ?40 c v ol (v) 0 0.6 0.4 0.2 002aaf111 5 10 15 i ol (ma) 0 t = 85 c 25 c ?40 c
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 80 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller conditions: v dd(reg)(3v3) = v dd(3v3) = 3.3 v; standard port pins. fig 15. typical pull-up current i pu versus input voltage v i conditions: v dd(reg)(3v3) = v dd(3v3) = 3.3 v; standard port pins. fig 16. typical pull-down current i pd versus input voltage v i 0 5 4 23 1 002aaf108 ?30 ?50 ?10 10 i pu (a) ?70 t = 85 c 25 c ?40 c v i (v) 002aaf109 v i (v) 0 5 3 24 1 10 70 50 30 90 i pd (a) ?10 t = 85 c 25 c ?40 c
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 81 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 11. dynamic characteristics 11.1 flash memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes from ram to the flash. data must be written to the flash in blocks of 256 bytes. [1] eeprom clock frequency = 375 khz. programming/eras e times increase with decreasing eeprom clock frequency. table 13. flash characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 - - years unpowered 20 - - years t er erase time sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms table 14. eeprom characteristics t amb = ? 40 ? cto+85 ? c; v dd(reg)(3v3) = 2.7 v to 3.6 v. symbol parameter conditions min typ max unit f clk clock frequency 200 375 400 khz n endu endurance 100000 500000 - cycles t ret retention time powered 10 - - years unpowered 10 - - years t er erase time 64 bytes [1] -1 . 8 -m s t prog programming time 64 bytes [1] -1 . 1 -m s
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 82 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 11.2 external memory interface table 15. dynamic characteristics: static external memory interface c l =10pf, t amb = ? 40 ? c to 85 ? c, v dd(3v3) = 3.0 v to 3.6 v. values guaranteed by design. symbol parameter [1] conditions [1] min max unit read cycle parameters [2] t cslav cs low to address valid time rd 1 1.4 2.5 ns t csloel cs low to oe low time rd 2 [3] 1.3 + t cy(clk) ? waitoen 2.5 + t cy(clk) ? waitoen ns t cslblsl cs low to bls low time rd 3 ; pb = 1 [3] 1.5 3.0 ns t oeloeh oe low to oe high time rd 4 [3] (waitrd ? waitoen + 1) ? t cy(clk) ? 1.0 (waitrd ? waitoen + 1) ? t cy(clk) ? 1.6 ns t am memory access time rd 5 [4] [3] (waitrd ? waitoen +1) ? t cy(clk) ? 7.2 (waitrd ? waitoen +1) ? t cy(clk) ? 15.5 ns t h(d) data input hold time rd 6 [5] [3] 0.1 0.1 ns t cshblsh cs high to bls high time pb = 1 1.5 3.0 ns t cshoeh cs high to oe high time [3] 1.3 2.5 ns t oehanv oe high to address invalid time [3] 0.09 0.13 ns t deact deactivation time rd 7 [3] ? 1.4 ? 2.5 ns write cycle parameters [2] t cslav cs low to address valid time wr 1 1.4 2.5 ns t csldv cs low to data valid time wr 2 1.5 2.9 ns t cslwel cs low to we low time wr 3 ; pb =1 [3] 1.4 + t cy(clk) ? (1 + waitwen) 2.5 + t cy(clk) ? (1 + waitwen) ns t cslblsl cs low to bls low time wr 4 ; pb = 1 [3] 3.0 3.0 ns t welweh we low to we high time wr 5 ; pb =1 [3] (waitwr ? waitwen + 1) ? t cy(clk) ? 1.0 (waitwr ? waitwen + 1) ? t cy(clk) ? 1.7 ns t blslblsh bls low to bls high time pb = 1 [3] (waitwr ? waitwen + 3) ? t cy(clk) ? 1.4 (waitwr ? waitwen + 3) ? t cy(clk) ? 2.7 ns t wehdnv we high to data invalid time wr 6 ; pb =1 [3] 1.2 + t cy(clk) 2.1 + t cy(clk) ns t weheow we high to end of write time wr 7 ; pb = 1 [6] [3] t cy(clk) ? 1.4 t cy(clk) ? 2.5 ns t blshdnv bls high to data invalid time pb = 1 1.4 2.7 ns t wehanv we high to address invalid time pb = 1 [3] 1 + t cy(clk) 1.7 + t cy(clk) ns t deact deactivation time wr 8 ; pb = 0; pb = 1 [3] ? 1.4 ? 2.5 ns t cslblsl cs low to bls low wr 9 ; pb = 0 [3] 3.0 + t cy(clk) ?? (1 + waitwen) 3.0 + t cy(clk) ?? (1 + waitwen) ns
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 83 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [1] parameters are shown as rd n or wd n in figure 17 as indicated in the conditions column. [2] parameters specified for 40 % of v dd(3v3) for rising edges and 60 % of v dd(3v3) for falling edges. [3] t cy(clk) = 1/cclk (see lpc408x/7x user manual ). [4] latest of address valid, emc_csx low, emc_oe low, emc_blsx low (pb = 1). [5] after end of read (eor): earliest of emc_csx high, emc_oe high, emc_blsx high (pb = 1), address invalid. [6] end of write (eow): earliest of address invalid, emc_csx high, emc_blsx high (pb = 1). t blslblsh bls low to bls high time wr 10 ; pb = 0 [3] (waitwr ? waitwen + 3) ? t cy(clk) ? 1.4 (waitwr ? waitwen + 3) ? t cy(clk) ? 2.7 ns t blsheow bls high to end of write time wr 11 ; pb = 0 [6] [3] 1.3 + t cy(clk) 2.2 + t cy(clk) ns t blshdnv bls high to data invalid time wr12; pb = 0 [3] 1.4 + t cy(clk) 2.7 + t cy(clk) ns table 15. dynamic characteristics: static external memory interface ?continued c l =10pf, t amb = ? 40 ? c to 85 ? c, v dd(3v3) = 3.0 v to 3.6 v. values guaranteed by design. symbol parameter [1] conditions [1] min max unit fig 17. external static memory read/write access (pb = 0) rd 1 rd 5 rd 2 wr 2 wr 9 wr 12 wr 10 wr 11 rd 5 rd 5 rd 6 wr 8 wr 1 eor eow rd 7 rd 4 emc_ax emc_csx emc_oe emc_blsx emc_we emc_dx 002aag214
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 84 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller fig 18. external static memory read/write access (pb =1) rd 1 wr 1 emc_ax wr 8 wr 4 wr 8 emc_csx rd 2 rd 7 rd 7 rd 4 emc_oe emc_blsx emc_we rd 5 wr 6 wr 2 rd 5 rd 5 rd 5 rd 6 rd 3 eor eow emc_dx wr 3 wr 5 wr 7 002aag215 fig 19. external static memory burst read cycle rd 5 rd 5 rd 5 rd 5 emc_ax emc_csx emc_oe emc_blsx emc_we emc_dx 002aag216 table 16. dynamic characteristi cs: dynamic external memory interface, read strategy bits (rd bits) = 00 c l =10pf, t amb = ? 40 ? c to 85 ? c, v dd(3v3) = 3.0 v to 3.6 v. all programmable delays emcdlyctl are bypassed. values guaranteed by design. symbol parameter min max unit common to read and write cycles t cy(clk) clock cycle time [1] 12.5 - ns t d(sv) chip select valid delay time 2.9 6.2 ns t h(s) chip select hold time 1.2 3.3 ns t d(rasv) row address strobe valid delay time 2.8 6.2 ns t h(ras) row address strobe hold time 1.3 3.5 ns t d(casv) column address strobe valid delay time 2.8 6.2 ns
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 85 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [1] refers to sdram clock signal emc_clkx. [2] the data input set-up time has to be selected with the following margin: t su(d) + delay time of feedback clock ? sdram access time ? board delay time ? 0. [3] the data input hold time has to be selected with the following margin: t h(d) + sdram access time ? board delay time ? delay time of feedback clock ? 0. t h(cas) column address strobe hold time 1.3 3.5 ns t d(wv) write valid delay time 3.6 7.7 ns t h(w) write hold time 1.6 4.2 ns t d(av) address valid delay time 3.4 7.4 ns t h(a) address hold time 1.1 3.0 ns read cycle parameters t su(d) data input set-up time [2] 5.3 1.5 ns t h(d) data input hold time [3] 3.7 5.2 ns write cycle parameters t d(qv) data output valid delay time 3.9 8.7 ns t h(q) data output hold time 0.2 1.6 ns table 17. dynamic characteristi cs: dynamic external memory interface, read strategy bits (rd bits) = 01 c l =10pf, t amb = ? 40 ? c to 85 ? c, v dd(3v3) = 3.0 v to 3.6 v. all programmable delays emcdlyctl are bypassed. values guaranteed by design. symbol parameter min max unit common to read and write cycles t cy(clk) clock cycle time [1] 12.5 - ns t d(sv) chip select valid delay time 2.7 6.0 ns t h(s) chip select hold time 1.0 3.1 ns t d(rasv) row address strobe valid delay time 2.7 6.0 ns t h(ras) row address strobe hold time 1.1 3.3 ns t d(casv) column address strobe valid delay time 2.7 6.1 ns t h(cas) column address strobe hold time 1.2 3.3 ns t d(wv) write valid delay time 3.2 7.1 ns t h(w) write hold time 1.6 4.2 ns t d(av) address valid delay time 3.3 7.3 ns t h(a) address hold time 1.0 2.8 ns read cycle parameters t su(d) data input set-up time [2] 5.3 1.5 ns t h(d) data input hold time [3] 3.7 5.2 ns write cycle parameters t d(qv) data output valid delay time 3.3 7.3 ns t h(q) data output hold time 0.2 1.6 ns table 16. dynamic characteristi cs: dynamic external memory interface, read strategy bits (rd bits) = 00 ?continued c l =10pf, t amb = ? 40 ? c to 85 ? c, v dd(3v3) = 3.0 v to 3.6 v. all programmable delays emcdlyctl are bypassed. values guaranteed by design. symbol parameter min max unit
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 86 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [1] refers to sdram clock signal emc_clkx. [2] the data input set-up time has to be selected with the following margin: t su(d) + delay time of feedback clock ? sdram access time ? board delay time ? 0. [3] the data input hold time has to be selected with the following margin: t h(d) + sdram access time - board delay time - delay time of feedback clock ? 0. [1] the programmable delay blocks are controlled by the emcdlyctl register in the emc register block. all delay times are incremental delays for each el ement starting from delay block 0. see the lpc408x/7x user manual for details. fig 20. dynamic external memory interface signal timing 002aah129 t cy(clk) emc_clkn delay = 0 emc_dycsn, emc_ras, emc_cas, emc_we, emc_ckeoutn, emc_a[22:0], emc_dqmoutn t h(q) t h(d) t su(d) emc_d[31:0] write emc_d[31:0] read t d(qv) t h(x) t d(xv) table 18. dynamic characteristics: dynami c external memory interface programmable clock delays c l =10pf, t amb = ? 40 ? c to 85 ? c, v dd(3v3) = 3.0 v to 3.6 v.values guaranteed by design. symbol parameter conditions min max unit t d delay time programmable delay block 0 (cmddly or clkoutndly bit 0 = 1) [1] 0.1 0.2 ns programmable delay block 1 (cmddly or clkoutndly bit 1 = 1) [1] 0.2 0.5 ns programmable delay block 2 (cmddly or clkoutndly bit 2 = 1) [1] 0.5 1.3 ns programmable delay block 3 (cmddly or clkoutndly bit 3 = 1) [1] 1.2 2.9 ns programmable delay block 4 (cmddly or clkoutndly bit 4 = 1) [1] 2.4 6.0 ns
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 87 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 11.3 external clock [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. 11.4 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. 11.5 i/o pins [1] applies to standard port pins and reset pin. for details, see the lpc408x/7x ibis model available on the nxp website. table 19. dynamic characteristic: external clock (see figure 37 ) t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4--ns t clcx clock low time t cy(clk) ? 0.4--ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns fig 21. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907 table 20. dynamic characteristic: internal oscillators t amb = ? 40 ? c to +85 ? c; 2.7 v ? v dd(3v3) ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz f i(rtc) rtc input frequency - - 32.768 - khz table 21. dynamic characteristic: i/o pins [1] t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 88 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 11.6 ssp interface table 22. dynamic characteristics: ssp pins in spi mode c l =10pf, t amb = ? 40 ? c to 85 ? c, v dd(3v3) = 3.0 v to 3.6 v. values guaranteed by design. symbol parameter conditions min max unit ssp master t cy(clk) clock cycle time full-duplex mode [1] 30 - ns when only transmitting 30 - ns t ds data set-up time in spi mode [2] 14.8 - ns t dh data hold time in spi mode [2] 2- n s t v(q) data output valid time in spi mode [2] -6 . 3n s t h(q) data output hold time in spi mode [2] ? 2.4 - ns
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 89 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [1] t cy(clk) = (sspclkdiv ? (1 + scr) ? cpsdvsr) / f main . 1the clock cycle time derived from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the ssp peripheral clock divider (sspclkdiv), the ssp scr parameter (specified in the ssp0cr0 regi ster), and the ssp cpsdvsr parameter (specified in the ssp clock prescale register). [2] t amb = ?40 ? c to 85 ? c; v dd(3v3) = 3.0 v to 3.6 v. [3] t cy(clk) = 12 ? t cy(pclk) . [4] t amb = 25 ? c; v dd(3v3) = 3.3 v. ssp slave t cy(pclk) pclk cycle time 10 ns t cy(clk) clock cycle time [3] 120 - ns t ds data set-up time in spi mode [3] [4] 14.8 - ns t dh data hold time in spi mode [3] [4] 2- n s t v(q) data output valid time in spi mode [3] [4] -6 . 3n s t h(q) data output hold time in spi mode [3] [4] ? 2.4 - ns fig 22. ssp master timing in spi mode table 22. dynamic characteristics: ssp pins in spi mode c l =10pf, t amb = ? 40 ? c to 85 ? c, v dd(3v3) = 3.0 v to 3.6 v. values guaranteed by design. symbol parameter conditions min max unit sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 90 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 11.7 i 2 c-bus fig 23. ssp slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830 table 23. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ? c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 91 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the falling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with respect to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the lo w period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. also the acknowledge timing must meet this set-up time. t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns table 23. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ? c. [2] symbol parameter conditions min max unit fig 24. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 92 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 11.8 i 2 s-bus interface [1] cclk = 100 mhz; peripheral clock to the i 2 s-bus interface pclk = cclk / 4. i 2 s clock cycle time t cy(clk) = 1600 ns, corresponds to the sck signal in the i 2 s-bus specification . table 24. dynamic characteristics: i 2 s-bus interface pins c l =10pf, t amb = ? 40 ? c to 85 ? c, v dd(3v3) = 3.0 v to 3.6 v. values guaranteed by design. symbol parameter conditions min max unit common to input and output t r rise time [1] -6.7ns t f fall time [1] -8.0ns t wh pulse width high on pins i2s_tx_sck and i2s_rx_sck [1] 25 - - t wl pulse width low on pins i2s_tx_sck and i2s_rx_sck [1] -25ns output t v(q) data output valid time on pin i2s_tx_sda; [1] -6ns input t su(d) data input set-up time on pin i2s_rx_sda [1] 5- ns t h(d) data input hold time on pin i2s_rx_sda [1] 2- ns fig 25. i 2 s-bus timing (transmit) 002aag202 i2s_tx_sck i2s_tx_sda i2s_tx_ws t cy(clk) t f t r t wh t wl t v(q) t v(q)
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 93 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 11.9 lcd remark: the lcd controller is available on parts lpc4088. 11.10 sd/mmc remark: the sd/mmc card interface is available on parts lpc4088/78/76. fig 26. i 2 s-bus timing (receive) 002aag203 t cy(clk) t f t r t wh t su(d) t h(d) t su(d) t su(d) t wl i2s_rx_sck i2s_rx_sda i2s_rx_ws table 25. dynamic characteristics: lcd c l =10pf, t amb = ? 40 ? c to 85 ? c, v dd(3v3) = 3.0 v to 3.6 v. values guaranteed by design. symbol parameter conditions min max unit f clk clock frequency on pin lcd_dclk - 50 mhz t d(qv) data output valid delay time - 12 ns t h(q) data output hold time ? 0.5 - ns the lcd panel clock is shown with the default pola rity. the clock can be inverted via the ipc bit in the lcd_pol register. typically, the lcd panel uses the falling edge of the lcd_dclk to sample the data. fig 27. lcd timing 002aah325 lcd_dclk t d(qv) t cy(clk) t h(q) lcd_vd[n]
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 94 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 12. characteristics of the analog peripherals 12.1 adc electrical characteristics table 26. dynamic characteristics: sd/mmc c l =10pf, t amb = ? 40 ? c to 85 ? c, v dd(3v3) = 3.0 v to 3.6 v. values guaranteed by design. symbol parameter conditions min max unit f clk clock frequency on pin sd_clk; data transfer mode - 25 mhz on pin sd_clk; identification mode 25 mhz t su(d) data input set-up time on pins sd_cmd, sd_dat[3:0] as inputs 6- ns t h(d) data input hold time on pins sd_cmd, sd_dat[3:0] as inputs 6- ns t d(qv) data output valid delay time on pins sd_cmd, sd_dat[3:0] as outputs -23ns t h(q) data output hold time on pins sd_cmd, sd_dat[3:0] as outputs 3.5 - ns fig 28. sd/mmc timing 002aag204 sd_clk sd_datn (o) sd_datn (i) t d(qv) t h(d) t su(d) t cy(clk) t h(q) sd_cmd (o) sd_cmd (i) table 27. 12-bit adc characteristics v dda = 2.7 v to 3.6 v; t amb = ? 40 ? c to +85 ? c unless otherwise specified. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v 12-bit resolution; 400 ksamples/sec e d differential linearity error [1] [2] [3] --? 1lsb e l(adj) integral non-linearity [1] [4] --? 6lsb e o offset error [1] [5] --? 5lsb e g gain error [1] [6] --? 5lsb e t absolute error [1] [7] --< ?? 8lsb f clk(adc) adc clock frequency - - 12.4 mhz f c(adc) adc conversion frequency --400khz
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 95 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [1] conditions: v ssa =0v, v dda =3.3v. [2] the adc is monotonic, there are no missing codes. [3] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 29 . [4] the integral non-linearity (e l(adj) ) is the peak difference between the c enter of the steps of the actual and the ideal transfer curve after appropriate adj ustment of gain and offset errors. see figure 29 . [5] the offset error (e o ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. see figure 29 . [6] the gain error (e g ) is the relative difference in percent betw een the straight line fitting the actual transfer curve after removing offset error, and the strai ght line which fits the ideal transfer curve. see figure 29 . [7] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 29 . [8] see figure 30 . [9] 8-bit resolution is achieved by ignoring the lower four bits of the adc conversion result. c ia analog input capacitance --5pf r vsi voltage source interface resistance [8] --1k ? 8-bit resolution [9] ; 1.16 msamples/sec e d differential linearity error [1] [2] [3] - ? 1- lsb e l(adj) integral non-linearity [1] [4] - ? 1- lsb e o offset error [1] [5] - ? 1- lsb e g gain error [1] [6] - ? 1- lsb e t absolute error [1] [7] --< ?? 1.5 lsb f clk(adc) adc clock frequency - - 36 mhz f c(adc) adc conversion frequency --1.16mhz c ia analog input capacitance --5pf r vsi voltage source interface resistance [8] --1k ? table 27. 12-bit adc characteristics ?continued v dda = 2.7 v to 3.6 v; t amb = ? 40 ? c to +85 ? c unless otherwise specified. symbol parameter conditions min typ max unit
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 96 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 29. 12-bit adc characteristics 002aaf436 4095 4094 4093 4092 4091 (2) (1) 4096 4090 4091 4092 4093 4094 4095 7 123456 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 lsb (ideal) code out vrefp - v ss 4096 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 97 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 12.2 dac electrical characteristics 12.3 comparator electr ical characteristics the values of resistor components r cmp and r sw vary with temperature and input voltage and are process-dependent. fig 30. adc interface to pins adc0_in[n] table 28. adc interface components component range description r cmp 90 ? to 300 ? switch-on resistance for the comp arator input switch. varies with temperature, input voltage, and process. r sw 500 ? to 2 k ? switch-on resistance for channel selection switch. varies with temperature, input voltage, and process. c1 110 ff parasitic capacitance from the adc block level. c2 80 ff parasitic capacitance from the adc block level. c3 1.6 pf sampling capacitor. lpc408x/7x ad0[n] 110 ff 80 ff c ia 1.6 pf r vsi r sw 500 - 2 k r cmp 90 - 300 v ss v ext 002aah275 adc comparator block c1 c3 c2 table 29. 10-bit dac electr ical characteristics v dda = 2.7 v to 3.6 v; t amb = ? 40 ? c to +85 ? c unless otherwise specified symbol parameter conditions min typ max unit e d differential linearity error - ? 1- lsb e l(adj) integral non-linearity - ? 1.5 - lsb e o offset error - 0.6 - % e g gain error - 0.6 - % c l load capacitance - - 200 pf r l load resistance 1 - - k ?
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 98 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [1] c l = 10 pf; results from measurements on silicon samples ov er process corners and over the full temperature range t amb = -40 ? c to +85 ? c. [2] input hysteresis is relative to the referenc e input channel and is software programmable. table 30. comparator characteristics v dda = 3.0 v and t amb = 25 ? c unless noted otherwise. symbol parameter conditions min typ max unit static characteristics i dd supply current - 55 - ? a v ic common-mode input voltage 0 - v dda v dv o output voltage variation 0 - v dda v v offset offset voltage v ic = 0.1 v - ? 4 to +4.2 - mv v ic = 1.5 v - ? 2-mv v ic = 2.8 v - ? 2.5 mv dynamic characteristics t startup start-up time nominal process - 4 - ? s t pd propagation delay high to low; v dda = 3.3 v; v ic = 0.1 v; 50 mv overdrive input [1] 122 130 142 ns v ic = 0.1 v; rail-to-rail input [1] 173 189 233 ns v ic = 1.5 v; 50 mv overdrive input [1] 101 108 119 ns v ic = 1.5 v; rail-to-rail input [1] 114 127 162 ns v ic = 2.9 v; 50 mv overdrive input [1] 123 134 143 ns v ic = 2.9 v; rail-to-rail input [1] 79 91 120 ns t pd propagation delay low to high; v dda = 3.3 v; v ic = 0.1 v; 50 mv overdrive input [1] 221 232 254 ns v ic = 0.1 v; rail-to-rail input [1] 59 63 68 ns v ic = 1.5 v; 50 mv overdrive input [1] 183 229 249 ns v ic = 1.5 v; rail-to-rail input [1] 147 174 213 ns v ic = 2.9 v; 50 mv overdrive input [1] 171 192 216 ns v ic = 2.9 v; rail-to-rail input [1] 235 305 450 ns v hys hysteresis voltage positive hysteresis; v dda = 3.0 v; v ic = 1.5 v [2] - 5, 10, 20 - mv v hys hysteresis voltage negative hysteresis; v dda = 3.0 v; v ic = 1.5 v [2] - 5, 10, 20 - mv r lad ladder resistance - - 1.034 - m ?
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 99 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller [1] maximum values are derived fr om worst case simulation (v dda = 2.6 v; t amb = 85 ? c; slow process models). [2] settling time applies to switching between comparator and adc channels. [1] measured on typical silicon samples wi th a 2 khz input signal and overdrive < 100 ? v. power switched off to all analog peripherals except the comparator. table 31. comparator voltage ladder dynamic characteristics symbol parameter conditions min typ max unit t s(pu) power-up settling time to 99% of voltage ladder output value [1] -- 30 ? s t s(sw) switching settling time to 99% of voltage ladder output value [1] [2] -- 15 ? s table 32. comparator voltage ladder reference static characteristics v dda = 3.3 v; t amb = -40 ? c to + 85 ? c. symbol parameter conditions min typ max [1] unit e v(o) output voltage error internal v dda supply decimal code = 00 0 0 0 % decimal code = 08 ? 0.45 ? 0.5 ? 0.55 % decimal code = 16 ? 0.99 ? 1.1 ? 1.21 % decimal code = 24 ? 1.26 ? 1.4 ? 1.54 % decimal code = 30 ? 1.35 ? 1.5 ? 1.65 % decimal code = 31 ? 1.35 ? 1.5 ? 1.65 % e v(o) output voltage error external vddcmp supply decimal code = 00 0 0 0 % decimal code = 08 0.44 0.4 0.36 % decimal code = 16 ? 0.18 ? 0.2 ? 0.22 % decimal code = 24 ? 0.45 ? 0.5 ? 0.55 % decimal code = 30 ? 0.54 ? 0.6 ? 0.66 % decimal code = 31 ? 0.45 ? 0.5 ? 0.55 %
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 100 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 13. application information 13.1 suggested usb interface solutions remark: the usb controller is available as a device/host/otg controller on parts lpc4088 and lpc4078/76 and as device-only controller on parts lpc4074/72. fig 31. usb interface on a self-powered device lpc40xx usb-b connector usb_d+ usb_connect softconnect switch usb_d- v bus v ss v dd(3v3) r1 1.5 k r s = 33 r s = 33 usb_up_led fig 32. usb interface on a bus-powered device lpc40xx v dd(3v3) r1 1.5 k r2 usb_up_led 002aah268 usb-b connector usb_d+ usb_d- v bus v ss r s = 33 r s = 33
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 101 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller fig 33. usb otg port configuration: port 1 otg dual-role device, port 2 host usb_up_led1 usb_d+1 usb_d-1 usb_pwrd2 usb_sda1 usb_scl1 rstout 15 k 15 k lpc408x/7x usb-a connector mini-ab connector 33 33 33 33 v dd v dd v dd usb_up_led2 v dd usb_ovrcr2 lm3526-l ena in 5 v outa flaga v dd d+ d- v bus usb_ppwr2 usb_d+2 usb_d-2 002aah269 r7 r4 r5 r6 r1 r2 r3 r4 r8 usb_int1 reset_n adr/psw speed suspend oe_n/int_n scl sda int_n v bus id dp dm isp1302 v ssio, v sscore v ssio, v sscore
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 102 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller fig 34. usb otg port configuration: vp_vm mode usb_tx_dp1 usb_tx_dm1 usb_rcv1 usb_rx_dp1 usb_rx_dm1 usb_scl1 usb_sda1 speed adr/psw sda scl reset_n int_n vp vm suspend oe_n/int_n se0_vm dat_vp rcv v bus id dp dm lpc408x/7x isp1302 usb mini-ab connector 33 33 002aah270 usb_tx_e1 rstout v dd v dd usb_int1 usb_up_led1 v dd v ssio, v sscore
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 103 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller fig 35. usb host port configuration: port 1 and port 2 as hosts usb_up_led1 usb_d+1 usb_d-1 usb_pwrd1 usb_pwrd2 15 k 15 k 15 k 15 k lpc408x/7x usb-a connector usb-a connector 33 33 33 33 002aah271 v dd usb_up_led2 v dd usb_ovrcr1 usb_ovrcr2 usb_ppwr1 lm3526-l ena enb in 5 v flaga outa outb flagb v dd v dd d+ d- d+ d- v bus v bus usb_ppwr2 usb_d+2 usb_d-2 v ssio, v sscore v ssio, v sscore
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 104 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 13.2 crystal oscillator xtal input and component selection the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. fig 36. usb device port configuration: port 1 host and port 2 device usb_up_led1 usb_d+1 usb_d-1 usb_pwrd1 15 k 15 k lpc408x/7x usb-a connector usb-b connector 33 33 33 33 002aah272 v dd usb_up_led2 usb_connect2 v dd v dd usb_ovrcr1 usb_ppwr1 lm3526-l ena in 5 v flaga outa v dd d+ d- d+ d- v bus usb_d+2 usb_d-2 v bus v bus v ssio, v sscore v ssio, v sscore fig 37. slave mode operation of the on-chip oscillator lpc40xx xtal1 c i 100 pf c g 002aah273
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 105 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf ( figure 37 ), with an amplitude between 200 mv(rms) and 1000 mv(rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. external components and models used in oscillation mode are shown in figure 38 and in ta b l e 3 3 and ta b l e 3 4 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequenc y is represen ted by l, c l and r s ). capacitance c p in figure 38 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer. fig 38. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 33. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters): low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 /c x2 1 mhz - 5 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf 5 mhz - 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz - 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz - 20 mhz 10 pf < 80 ? 18 pf, 18 pf 002aah274 lpc40xx xtalin xtalout c x2 c x1 xtal = c l c p r s l
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 106 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 13.3 xtal printed-circuit boar d (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. 13.4 standard i/o pi n configuration figure 39 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver: open-drain mode enabled/disabled ? digital input: pull-up enabled/disabled ? digital input: pull-down enabled/disabled ? digital input: repeater mode enabled/disabled ? analog input the default configuration for standard i/o pi ns is input with pull-up enabled. the weak mos devices provide a drive capability equiva lent to pull-up and pull-down resistors. table 34. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters): high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , cx2 15 mhz - 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz - 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 107 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 13.5 reset pin configuration 13.6 reset pin configurat ion for rtc operation under certain circumstances, the rtc may temporarily pause and lose fractions of a second during the rising and falling edges of the reset signal. fig 39. standard i/o pin configuration with analog input pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable data output data input analog input select analog input 002aaf272 pin configured as digital output driver pin configured as digital input pin configured as analog input fig 40. reset pin configuration v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 108 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller to eliminate the loss of time counts in the rtc due to voltage swing or ramp rate of the reset signal, connect an rc filter between the reset pin and the external reset input. fig 41. reset input with rc filter 002aag552 external reset input 10 k 0.1 f reset pin
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 109 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 14. package outline fig 42. lqfp208 package unit a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.9 0.5 30.15 29.85 1.43 1.08 7 0 o o 0.080.12 1 0.08 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot459-1 136e30 ms-026 00-02-06 03-02-20 d (1) 28.1 27.9 h d 30.15 29.85 e z 1.43 1.08 d pin 1 index b p e e a 1 a l p detail x l (a ) 3 b 52 c d h b p e h a 2 v m b d z d a z e e v m a x 1 208 157 156 105 104 53 y w m w m 0 5 10 mm scale lqfp208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm sot459-1 a max. 1.6
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 110 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller fig 43. tfbga208 package references outline version european projection issue date iec jedec jeita sot950-1 - - - sot950-1 06-06-01 06-06-14 unit a max mm 1.2 0.4 0.3 0.8 0.6 15.1 14.9 15.1 14.9 0.8 12.8 0.15 0.08 0.1 a 1 dimensions (mm are the original dimensions) tfbga208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.7 mm 0 5 10 mm scale a 2 b 0.5 0.4 d e e e 1 e 2 12.8 v w y 0.12 y 1 c y c y 1 x b ball a1 index area e 2 e 1 e e ac b ? v m c ? w m a b c d e f h k g l j m n p r u t 246810121416 1357911131517 ball a1 index area b a d e detail x a a 2 a 1
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 111 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller fig 44. tfbga180 package 0.8 a 1 ba 2 unit d y e references outline version european projection issue date 03-03-03 06-03-14 iec jedec jeita mm 1.2 0.35 0.25 0.85 0.75 12.2 11.8 y 1 12.2 11.8 0.5 0.4 0.12 0.1 e 1 10.4 e 2 10.4 dimensions (mm are the original dimensions) sot570-2 e 0.15 v 0.08 w 0 5 10 mm scale sot570-2 tfbga180: thin fine-pitch ball grid array package; 180 balls; body 12 x 12 x 0.8 mm a max. a a 2 a 1 detail x e e x d e a b c d e f h g j k l m n p 246 9 8 1357 10 1314 1211 b a e 2 e 1 ball a1 index area ball a1 index area 1/2 e 1/2 e y y 1 c b c ac c b ? v m ? w m
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 112 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller fig 45. lqfp144 package unit a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 0.5 22.15 21.85 1.4 1.1 7 0 o o 0.080.2 0.08 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot486-1 136e23 ms-026 00-03-14 03-02-20 d (1) (1)(1) 20.1 19.9 h d 22.15 21.85 e z 1.4 1.1 d 0 5 10 mm scale b p e e a 1 a l p detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x y w m w m a max. 1.6 lqfp144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm sot486-1 108 109 pin 1 index 73 72 37 1 144 36
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 113 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller fig 46. lqfp80 package unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o o 0.15 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 sot315-1 136e15 ms-026 00-01-19 03-02-25 d (1) (1)(1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 114 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 15. soldering fig 47. reflow soldering of the lqfp208 package sot459-1 dimensions in mm occupied area footprint information for reflow soldering of lqfp208 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy p1 p2 c sot459-1_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout 31.300 31.300 28.300 28.300 0.500 0.560 0.280 1.500 0.400 28.500 28.500 31.550 31.550
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 115 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller fig 48. reflow soldering of the tfbga180 package dimensions in mm pslspsrhxhy hx hy sot570-2 solder land plus solder paste occupied area footprint information for reflow soldering of tfbga180 package solder land solder paste deposit solder resist p p sl sp sr generic footprint pattern refer to the package outline drawing for actual layout detail x see detail x sot570-2_fr 0.80 0.400 0.400 0.550 12.575 12.575
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 116 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller fig 49. reflow soldering of the lqfp144 package sot486-1 dimensions in mm occupied area footprint information for reflow soldering of lqfp144 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy p1 p2 c sot486-1_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout 23.300 23.300 20.300 20.300 0.500 0.560 0.280 1.500 0.400 20.500 20.500 23.550 23.550
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 117 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller fig 50. reflow soldering of the lqfp80 package sot315-1 dimensions in mm occupied area footprint information for reflow soldering of lqfp80 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 15.300 15.300 12.300 12.300 p1 0.500 p2 0.560 0.280 c 1.500 0.400 12.500 12.500 15.550 15.550 sot315-1_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 118 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 16. abbreviations table 35. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brownout detection can controller area network dac digital-to-analog converter dma direct memory access eop end of packet etm embedded trace macrocell gpio general purpose input/output gps global positioning system hvac heating, venting, and air conditioning irc internal rc irda infrared data association jtag joint test action group mac media access control miim media independent interface management ohci open host controller interface otg on-the-go phy physical layer plc programmable logic controller pll phase-locked loop pwm pulse width modulator rmii reduced media independent interface se0 single ended zero spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port tcm tightly coupled memory ttl transistor-transistor logic uart universal asynchronous receiver/transmitter usb universal serial bus
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 119 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 17. revision history table 36. revision history document id release date data sheet status change notice supersedes lpc408x_7x v.1 20120917 objective data sheet - -
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 120 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 121 of 123 nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc408x_7x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1 ? 17 september 2012 122 of 123 continued >> nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 ordering information . . . . . . . . . . . . . . . . . . . . . 5 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 8 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 functional description . . . . . . . . . . . . . . . . . . 39 7.1 architectural overview . . . . . . . . . . . . . . . . . . 39 7.2 arm cortex-m4 processor . . . . . . . . . . . . . . . 39 7.3 arm cortex-m4 floating point unit (fpu) . . . 39 7.4 on-chip flash program memo ry . . . . . . . . . . . 39 7.5 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.6 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 40 7.7 memory protection unit (mpu). . . . . . . . . . . . 40 7.8 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.9 nested vectored interrupt controller (nvic) . 43 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.9.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 43 7.10 pin connect block . . . . . . . . . . . . . . . . . . . . . . 43 7.11 external memory controll er (emc). . . . . . . . . 43 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.12 general purpose dma controller . . . . . . . . . . 45 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.13 crc engine . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.14 lcd controller. . . . . . . . . . . . . . . . . . . . . . . . . 46 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.15 ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.16 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.16.1 usb device controller . . . . . . . . . . . . . . . . . . . 48 7.16.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.16.2 usb host controller. . . . . . . . . . . . . . . . . . . . . 49 7.16.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.16.3 usb otg controller . . . . . . . . . . . . . . . . . . . . 49 7.16.3.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.17 sd/mmc card interface . . . . . . . . . . . . . . . . . 49 7.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.18 fast general purpose parallel i/o . . . . . . . . . . 50 7.18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.19 12-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.20 10-bit dac . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.21 comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.21.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.22 uart0/1/2/3 and usart4 . . . . . . . . . . . . . . 52 7.22.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.23 spifi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.23.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.24 ssp serial i/o controller. . . . . . . . . . . . . . . . . 53 7.24.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.25 i 2 c-bus serial i/o controllers . . . . . . . . . . . . . 53 7.25.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.26 i 2 s-bus serial i/o controllers . . . . . . . . . . . . . 54 7.26.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.27 can controller and acceptance filters . . . . . . 54 7.27.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.28 general purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 55 7.28.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.29 pulse width modulator (pwm). . . . . . . . . . . . 56 7.29.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.30 motor control pwm . . . . . . . . . . . . . . . . . . . . 57 7.31 quadrature encoder inte rface (qei) . . . . . . . 57 7.31.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.32 arm cortex-m4 system tick timer . . . . . . . . . 58 7.33 windowed watchdog ti mer (wwdt) . . . . . . 58 7.33.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.34 rtc and backup registers . . . . . . . . . . . . . . . 59 7.34.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.35 event monitor/recorder . . . . . . . . . . . . . . . . . 59 7.35.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.36 clocking and power control . . . . . . . . . . . . . . 60 7.36.1 crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 60 7.36.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 61 7.36.1.2 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 61 7.36.1.3 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 61 7.36.1.4 watchdog oscillator . . . . . . . . . . . . . . . . . . . . 61 7.36.2 main pll (pll0) and alternate pll (pll1) . 61 7.36.3 wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 62 7.36.4 power control . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.36.4.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.36.4.2 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 63 7.36.4.3 power-down mode . . . . . . . . . . . . . . . . . . . . . 64 7.36.4.4 deep power-down mode . . . . . . . . . . . . . . . . 64 7.36.4.5 wake-up interrupt controller (wic) . . . . . . . . 64 7.36.5 peripheral power control . . . . . . . . . . . . . . . . 65 7.36.6 power domains . . . . . . . . . . . . . . . . . . . . . . . 65 7.37 system control . . . . . . . . . . . . . . . . . . . . . . . . 66 7.37.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.37.2 brownout detection . . . . . . . . . . . . . . . . . . . . 67 7.37.3 code security (code read protection - crp) 67
nxp semiconductors lpc408x/7x 32-bit arm cortex-m4 microcontroller ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 17 september 2012 document identifier: lpc408x_7x please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 7.37.4 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.37.5 ahb multilayer matrix . . . . . . . . . . . . . . . . . . . 68 7.37.6 external interrupt inputs . . . . . . . . . . . . . . . . . 68 7.37.7 memory mapping control . . . . . . . . . . . . . . . . 68 7.38 debug control . . . . . . . . . . . . . . . . . . . . . . . . . 68 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 68 9 thermal characteristics . . . . . . . . . . . . . . . . . 70 10 static characteristics. . . . . . . . . . . . . . . . . . . . 72 10.1 power consumption . . . . . . . . . . . . . . . . . . . . 75 10.2 peripheral power consumpt ion . . . . . . . . . . . . 77 10.3 electrical pin characteristics . . . . . . . . . . . . . . 79 11 dynamic characteristics . . . . . . . . . . . . . . . . . 81 11.1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.2 external memory interface . . . . . . . . . . . . . . . 82 11.3 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.4 internal oscillators. . . . . . . . . . . . . . . . . . . . . . 87 11.5 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.6 ssp interface . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.7 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.8 i 2 s-bus interface . . . . . . . . . . . . . . . . . . . . . . . 92 11.9 lcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.10 sd/mmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12 characteristics of the analog peripherals . . . 94 12.1 adc electrical characteristics . . . . . . . . . . . . . 94 12.2 dac electrical characteristics . . . . . . . . . . . . 97 12.3 comparator electrical characteristics . . . . . . . 97 13 application information. . . . . . . . . . . . . . . . . 100 13.1 suggested usb interface solutions . . . . . . . 100 13.2 crystal oscillator xtal input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 13.3 xtal printed-circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.4 standard i/o pin configurat ion . . . . . . . . . . . 106 13.5 reset pin configuration . . . . . . . . . . . . . . . . . 107 13.6 reset pin configuration for rtc operation . . 107 14 package outline . . . . . . . . . . . . . . . . . . . . . . . 109 15 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 118 17 revision history . . . . . . . . . . . . . . . . . . . . . . . 119 18 legal information. . . . . . . . . . . . . . . . . . . . . . 120 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 120 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 120 18.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 121 19 contact information. . . . . . . . . . . . . . . . . . . . 121 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

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